LMK04828-EP Datasheet, PDF (4/102 Pages) Texas Instruments – Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

LMK04828-EP
SNAS703 – APRIL 2017
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DAP
PIN
I/O
NAME
SYNC/SYSREF_REQ
I
NC
Vcc1_VCO
LDObyp1
LDObyp2
SDCLKout3,
SDCLKout3*
O
DCLKout2,
DCLKout2*
O
Vcc2_CG1
CS*
I
SCK
I
SDIO
I/O
Vcc3_SYSREF
SDCLKout5,
SDCKLout5*
O
DCLKout4,
DCLKout4*
O
Vcc4_CG2
DCLKout6,
DCLKout6*
O
SDCLKout7,
SDCLKout7*
O
Status_LD1
I/O
CPout1
O
Vcc5_DIG
CLKin1, CLKin1*
I
FBCLKin,
FBCLKin*
I
Fin, Fin*
I
Vcc6_PLL1
CLKin0, CLKin0*
I
Vcc7_OSCout
OSCout, OSCout*
I/O
CLKin2, CLKin2*
Vcc8_OSCin
OSCin, OSCin*
I
Vcc9_CP2
CPout2
O
Vcc10_PLL2
Status_LD2
I/O
SDCLKout9,
SDCLKout9*
O
DCLKout8,
DCLKout8*
O
Vcc11_CG3
DCLKout10,
DCLKout10*
O
SDCLKout11,
SDCLKout11*
O
CLKin_SEL0
I/O
CLKin_SEL1
I/O
SDCLKout13,
SDCLKout13*
O
DCLKout12,
DCLKout12*
O
Vcc12_CG0
DAP
Pin Functions (continued)
TYPE
CMOS
PWR
ANLG
ANLG
Programmable
DESCRIPTION ⁽¹⁾
Synchronization input or SYSREF_REQ for requesting continuous SYSREF
Do not connect. These pins must be left floating.
Power supply for VCO LDO
LDO bypass, bypassed to ground with 10-µF capacitor.
LDO bypass, bypassed to ground with a 0.1-µF capacitor.
SYSREF or device clock output 3
Programmable
PWR
CMOS
CMOS
CMOS
PWR
Programmable
Device clock output 2
Power supply for clock outputs 2 and 3
Chip select
SPI clock
SPI data
Power supply for SYSREF divider and SYNC
SYSREF or device clock output 5
Programmable
PWR
Programmable
Device clock output 4
Power supply for clock outputs 4, 5, 6 and 7
Device clock output 6
Programmable
Programmable
ANLG
PWR
ANLG
ANLG
ANLG
PWR
ANLG
PWR
Programmable
PWR
ANLG
PWR
ANLG
PWR
Programmable
Programmable
SYSREF or device clock output 7
Programmable status pin
Charge pump 1 output
Power supply for the digital circuitry
Reference clock Input Port 1 for PLL1
Feedback input for external clock feedback input (0–delay mode)
External VCO input (external VCO mode)
Power supply for PLL1, charge pump 1, holdover DAC
Reference clock input port 0 for PLL1
Power supply for OSCout port
Buffered output of OSCin port
Reference clock Input Port 2 for PLL1
Power supply for OSCin
Feedback to PLL1, reference input to PLL2 — AC-coupled
Power supply for PLL2 charge pump
Charge pump 2 output
Power supply for PLL2
Programmable status pin
SYSREF or device clock 9
Programmable
PWR
Programmable
Device clock output 8
Power supply for clock outputs 8, 9, 10, and 11
Device clock output 10
Programmable
Programmable
Programmable
Programmable
SYSREF or device clock output 11
Programmable status pin
Programmable status pin
SYSREF or device clock output 13
Programmable
PWR
GND
Device clock output 12
Power supply for clock outputs 0, 1, 12, and 13
DIE ATTACH PAD, connect to GND
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