TMS320F28069_14 Datasheet, PDF (40/175 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
www.ti.com
2.6 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 2-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 2-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 2-10.
Peripheral Frame 3: McBSP registers are mapped to this. See Table 2-11.
Table 2-8. Peripheral Frame 0 Registers⁽¹⁾
NAME
Device Emulation Registers
System Power Control Registers
FLASH Registers⁽³⁾
Code Security Module Registers
ADC registers
(0 wait read only)
CPU–TIMER0, CPU–TIMER1, CPU–TIMER2
Registers
PIE Registers
PIE Vector Table
DMA Registers
CLA Registers
CLA to CPU Message RAM (CPU writes ignored)
CPU to CLA Message RAM (CLA writes ignored)
ADDRESS RANGE
0x00 0880 – 0x00 0984
0x00 0985 – 0x00 0987
0x00 0A80 – 0x00 0ADF
0x00 0AE0 – 0x00 0AEF
0x00 0B00 – 0x00 0B0F
0x00 0C00 – 0x00 0C3F
0x00 0CE0 – 0x00 0CFF
0x00 0D00 – 0x00 0DFF
0x00 1000 – 0x00 11FF
0x00 1400 – 0x00 147F
0x00 1480 – 0x00 14FF
0x00 1500 – 0x00 157F
SIZE (×16)
261
3
96
16
16
64
32
256
512
128
128
128
EALLOW PROTECTED⁽²⁾
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
NA
NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
40
Device Overview
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TMS320F28064 TMS320F28063 TMS320F28062