THS4281 Datasheet, PDF (4/43 Pages) Texas Instruments – VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER

THS4281
SLOS432B – APRIL 2004 – REVISED OCTOBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).⁽¹⁾
Supply voltage, V_S– to V_S+
Input voltage, V_I
Differential input voltage, V_ID
Output current, I_O
Continuous power dissipation
Maximum junction temperature, any condition, ⁽²⁾ T_J
Maximum junction temperature, continuous operation, long-term reliability⁽²⁾ T_J
Storage temperature, T_stg
MIN
MAX
16.5
±V_S ± 0.5
±2
±100
See Dissipation Ratings
Table
+150
125°
–65
150
UNIT
V
V
V
mA
°C
°C
°C
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device. recommended operating conditions.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
Machine Model (MM)
VALUE
±3500
±1500
±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
Supply voltage, (V_S+ and V_{S –})
Dual supply
Single supply
MIN
±1.35
2.7
MAX
±8.25
16.5
UNIT
V
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
DBV (SOT-23)
THS4281
D (SOIC)
DGK (VSSOP)
UNIT
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance ⁽²⁾
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5 PINS
154.4
115
31.4
14.7
31
N/A
8 PINS
126.6
69
64.7
20.5
64.3
N/A
8 PINS
192.5
77.7
112.8
14.6
111.3
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This data was taken using the JEDEC standard High-K test PCB.
4
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