TCA7408 Datasheet, PDF (4/25 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander with Interrupt Output, RESET, I/ODirection Registers, and Programmable Pull-up/Pull-down

TCA7408
SCPS235 – NOVEMBER 2011
SIMPLIFIED LOGIC DIAGRAM (POSITIVE LOGIC)
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Data From
Shift Reg.
Write PD/PU
Data From
Shift Reg.
Write PULL ENAB
Data From
Shift Reg.
Write OUT STATE
Data From
Shift Reg.
Write OUT HIGHZ
Data From
Shift Reg.
Write IO DIRECTION
Data From
Shift Reg.
Write INPUT DEFAULT
PDZ / PU
Register
DQ
OFF
QZ
PULL ENAB
Register
DQ
OFF
QZ
OUT STATE
Register
DQ
OFF
QZ
OUT HIGHZ
Register
DQ
OFF
QZ
IO DIR.
Register
DQ
OFF
QZ
IN DEFAULT
Register
DQ
OFF
QZ
PD/PU Data
PULL ENAB Data
OUT STATE Data
OUT HIGHZ Data
IO DIR Data
INPUT DEF STATE Data
VDD
INPUT STATUS Data
Data From
Shift Reg.
Write INT MASK
INT MASK
Register
DQ
OFF
QZ
INT STAT
Register
DQ
OFF
QZ
Q3
ESD
D1 Protection
Q1
Diode
R1 100k
GPIO
R2 _100k
Q2
ESD
D2 Protection
Diode
Q4
INT MASK Data
GND
To INTz
(One of ANDed 8)
INTERUPT STATUS Data
On power up or reset, all registers return to default values.
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the Output Port Register. In
this case, there are low impedance paths between the I/O pin and either V_CCP or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
Q4 is turned on at power-on to enable the pull down resistor. Q3 and Q4 are enabled accordingly to the
Pull-up/-down Select Register and the Pull-up/-down Enable Register.
When the GPIO-port is set as an output the input buffers are disabled such that the bus is allowed to float.
I²C INTERFACE
The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to V_CCI through a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high. After the Start condition, the device address byte is sent, most
significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop).
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