TCA7408 Datasheet, PDF (10/25 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander with Interrupt Output, RESET, I/ODirection Registers, and Programmable Pull-up/Pull-down

TCA7408
SCPS235 – NOVEMBER 2011
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INTERRUPT (INT) OUTPUT
An interrupt is generated by a rising or falling edge of the port inputs in the input mode. After time t_iv, the signal
INT is valid. Resetting the interrupt circuit is achieved by reading the Interrupt Status Register. Resetting occurs
in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Each change of the I/Os after resetting is detected and is transmitted as INT. The values in the interrupt
status register are sampled on the rising edge of SCL during the read address acknowledge. If an interrupt
occurs before this event, it will be reflected in this register in the next read cycle. If an interrupt occurs very close
to this event, it may be reflected in both the current and the next read cycle. At no point is a valid interrupt ever
missed.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Default State Register.
The INT output has an open-drain structure and requires a pullup resistor to V_CCP or V_CCI depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
BUS TRANSACTIONS
Data is exchanged between the master and TCA7408 through write and read commands.
Writes
Data is transmitted to the TCA7408 by sending the device address and setting the least significant bit (LSB) to a
logic 0. The command byte is sent after the address and determines which register receives the data that follows
the command byte. There is no limitation on the number of data bytes sent in one write transmission.
Figure 4. Write to Output state Register (Note: ADDR = 0)
Figure 5. Write to I/O Direction Register (Note: ADDR = 0)
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