OPA322 Datasheet, PDF (4/36 Pages) Texas Instruments – 20-MHz, Low-Noise, 1.8-V, RRI/O, CMOS Operational Amplifier with Shutdown

OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538E – JANUARY 2011 – REVISED JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: V_S = +1.8 V to +5.5 V, or ±0.9 V to ±2.75 V (continued)
Boldface limits apply over the specified temperature range, T_A = –40°C to +125°C.
At T_A = +25°C, R_L = 10 kΩ connected to V_S/2, V_CM = V_S/2, V_OUT = V_S/2, and SHDN_x = V_S+, unless otherwise noted.
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OUTPUT
Voltage output swing from
both rails
V_O
R_L = 10 kΩ
10
20
Over temperature
Short-circuit current
Capacitive load drive
Open-loop output resistance
POWER SUPPLY
R_L = 10 kΩ
I_SC
V_S = 5.5 V
C_L
R_O
I_O = 0 mA, f = 1 MHz
30
±65
See Typical Characteristics
90
Specified voltage range
Quiescent current per amplifier
OPA322, OPA322S
Over temperature
OPA2322, OPA2322S
Over temperature
OPA4322, OPA4322S
Over temperature
Power-on time
SHUTDOWN ⁽²⁾
Quiescent current, per amplifier
High voltage (enabled)
Low voltage (disabled)
Amplifier enable time (full
shutdown) ⁽³⁾
V_S
I_Q
I_O = 0 mA, V_S = +5.5 V
I_O = 0 mA, V_S = +5.5 V
I_O = 0 mA, V_S = +5.5 V
I_O = 0 mA, V_S = +5.5 V
I_O = 0 mA, V_S = +5.5 V
I_O = 0 mA, V_S = +5.5 V
I_O = 0 mA, V_S = +5.5 V
V_S+ = 0 V to 5 V, to 90% I_Q level
V_S = 1.8 V to 5.5 V
I_QSD
All amplifiers disabled, SHDN = V_S–
V_IH
Amplifier enabled
V_IL
Amplifier disabled
1.8
5.5
1.6
1.9
2
1.5
1.75
1.85
1.4
1.65
1.75
28
0.1
0.5
(V+) - 0.1
(V-) + 0.1
t_ON Full shutdown; G = 1, V_OUT = 0.9 × V_S/2 ⁽⁴⁾
10
Amplifier enable time (partial
shutdown) ⁽³⁾
Amplifier disable time⁽³⁾
SHDN pin input bias current (per pin)
TEMPERATURE
t_ON Partial shutdown; G = 1, V_OUT = 0.9 × V_S/2 ⁽⁴⁾
t_OFF
G = 1, V_OUT = 0.1 × V_S/2
V_IH = 5.0 V
V_IL = 0 V
6
3
0.13
0.04
Specified range
–40
+125
Operating range
–40
+150
UNIT
mV
mV
mA
Ω
V
mA
mA
mA
mA
mA
mA
μs
µA
V
V
µs
µs
µs
µA
µA
°C
°C
(2) Ensured by design and characterization; not production tested.
(3) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual OPA2322S having both channels A and B disabled (SHDN_A = SHDN_B = V_S–) and the quad
OPA4322S having all channels A to D disabled (SHDN_A/B = SHDN_C/D = V_S–). For partial shutdown, only one SHDN pin is exercised;
in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
4
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