OPA322 Datasheet, PDF (15/36 Pages) Texas Instruments – 20-MHz, Low-Noise, 1.8-V, RRI/O, CMOS Operational Amplifier with Shutdown

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OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538E – JANUARY 2011 – REVISED JUNE 2012
OVERLOAD RECOVERY TIME
Overload recovery time is the time required for the output of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly important in applications where small signals must be
amplified in the presence of large transients. Figure 35 and Figure 36 show the positive and negative overload
recovery times of the OPA322, respectively. In both cases, the time elapsed before the OPA322 comes out of
saturation is less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows
excellent signal rectification without distortion of the output signal.
3
1
V_S = ±2.75 V
2.5
G = -10
0.5
Output
Input
2
0
1.5
-0.5
1
-1
0.5
-1.5
0
Input
-0.5
-1
9.75
10
10.25
10.5
10.75
11
Time (250 ns/div)
Figure 35. Positive Recovery Time
-2
-2.5
-3
9.75
Output
V_S = ±2.75 V
G = -10
10
10.25
10.5
10.75
11
Time (250 ns/div)
Figure 36. Negative Recovery Time
SHUTDOWN FUNCTION
The SHDN (enable) pin function of the OPAx322S is referenced to the negative supply voltage of the operational
amplifier. A logic level high enables the op amp. A valid logic high is defined as voltage [(V+) – 0.1 V], up to (V+),
applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the enable pin.
The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply, independent of the
positive supply voltage. This pin should either be connected to a valid high or a low voltage or driven, and not left
as an open circuit.
The logic input is a high-impedance CMOS input. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown of
all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture
allows the OPAx322S to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (t_OFF) depends on loading conditions and increases with increased
load resistance. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to mid-
supply (V_S / 2) is required. If using the OPAx322S without a load, the resulting turn-off time is significantly
increased.
GENERAL LAYOUT GUIDELINES
The OPA322 is a wideband amplifier. To realize the full operational performance of the device, follow good high-
frequency printed circuit board (PCB) layout practices. The bypass capacitors must be connected between each
supply pin and ground as close to the device as possible. The bypass capacitor traces should be designed for
minimum inductance.
LEADLESS DFN PACKAGE
The OPA2322 uses the DFN style package (also known as SON), which is a QFN with contacts on only two
sides of the package bottom. This leadless package maximizes PCB space and offers enhanced thermal and
electrical characteristics through an exposed pad. One of the primary advantages of the DFN package is its low
height (0,8 mm).
DFN packages are physically small, and have a smaller routing area. Additionally, they offer improved thermal
performance, reduced electrical parasitics, and a pinout scheme that is consistent with other commonly-used
packages (such as SO and MSOP). The absence of external leads also eliminates bent-lead issues.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S