LMX2430_14 Datasheet, PDF (4/48 Pages) Texas Instruments – PLLatinum™ Dual High Frequency Synthesizer for RF Personal Communications

LMX2430, LMX2433, LMX2434
SNAS187B – MAY 2004 – REVISED MAY 2004
Pin No.
UTCSP
6
Pin No.
TSSOP
7
Pin Name
OSCout/
FLoutIF
7
8
OSCin
8
9
Vcc
9
10
Ftest/LD
10
11
FLoutRF
11
12
GND
12
13
CPoutRF
13
14
GND
14
15
FinRF
15
16
FinRF*
16
17
Vcc
17
18
LE
18
19
19
20
20
1
CLK
DATA
Vcc
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Pin Descriptions (continued)
I/O
Description
O
Oscillator output/ IF PLL Fastlock output. The output configuration is dependent on
the state of the ENosc pin. When ENosc is set LOW, the pin functions as an IF
Fastlock output, which connects a resistor in parallel to R2 of the external loop filter.
This configuration also functions as a general purpose CMOS TRI-STATE output.
When ENosc is set HIGH, the pin functions as an oscillator output so that an
external crystal can be used.
I
Reference oscillator input. The input has an approximate Vcc/2 threshold and is
driven by an external AC coupled source.
—
Power supply bias for the RF PLL digital circuits and oscillator circuits. Vcc may
range from 2.25V to 2.75V. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
O
Programmable multiplexed output. Functions as a general purpose CMOS TRI-
STATE output, N and R divider output, RF/ IF PLL push-pull analog lock detect
output, RF/ IF PLL open-drain analog lock detect output, or RF/ IF PLL digital filtered
lock detect output.
O
RF PLL Fastlock output. This pin connects a resistor in parallel to R2 of the external
loop filter. This pin can also function as a general purpose CMOS TRI-STATE
output.
—
Ground for the RF PLL digital circuits.
O
RF PLL charge pump output. The output is connected to the external loop filter,
which drives the input of the RF VCO.
—
Ground for the RF PLL analog circuits.
I
RF PLL prescaler input. Small signal input from the VCO.
I
RF PLL prescaler complementary input. For single ended operation, this pin should
be AC grounded through a 100 pF capacitor. The LMX243x can be driven
differentially when the AC coupled capacitor is omitted.
—
Power supply bias for the RF PLL analog circuits. Vcc may range from 2.25V to
2.75V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
I
MICROWIRE Latch Enable input. High impedance CMOS input. When LE
transitions HIGH, DATA stored in the shift register is loaded into one of 6 internal
control registers.
I
MICROWIRE Clock input. High impedance CMOS input. DATA is clocked into the
24-bit shift register on the rising edge of CLK.
I
MICROWIRE Data input. High impedance CMOS input. Binary serial data. The MSB
of DATA is shifted in first. The two last bits are the control bits.
—
Power supply bias for the IF PLL analog and digital circuits, MICROWIRE, and
Ftest/LD circuits. Vcc may range from 2.25V to 2.75V. Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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