LMX2430_14 Datasheet, PDF (27/48 Pages) Texas Instruments – PLLatinum™ Dual High Frequency Synthesizer for RF Personal Communications

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Phase Comparator and Internal Charge Pump Characteristics
LMX2430, LMX2433, LMX2434
SNAS187B – MAY 2004 – REVISED MAY 2004
Notes:
1. The minimum width of the pump-up and pump-down current pulses occur at the CPoutRF or CPoutIF
pins when the loop is phase locked.
2. The diagram assumes positive VCO characteristics, i.e. RF_CPP or IF_CPP = 1.
3. f_r is the PFD input from the reference divider (R counter).
4. f_p is the PFD input from the programmable feedback divider (N counter).
5. CPout refers to either the RF or IF charge pump output.
CHARGE PUMPS
The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a
stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control
voltage towards Vcc during pump-up events and towards GND during pump-down events. When locked,
CPoutRF or CPoutIF are primarily in a TRI-STATE mode with small corrections occuring at the phase
comparator rate. The charge pump output current magnitude can be selected by toggling the RF_CPG or
IF_CPG control bits.
MICROWIRE SERIAL INTERFACE
The programmable register set is accessed via the MICROWIRE serial interface. A low voltage logic interface
allows direct connection to 1.8V devices. The interface is comprised of three signal pins: CLK, DATA and LE.
Serial data is clocked into the 24-bit shift register on the rising edge of CLK. The last two bits decode the internal
control register address. When LE transitions HIGH, DATA stored in the shift register is loaded into one of four
control registers depending on the state of the address bits. The MSB of DATA is loaded in first. The
synthesizers can be programmed even in power down mode. A complete programming description is provided in
Programming Description.
MULTI-FUNCTION OUTPUTS
The LMX243x device's Ftest/LD output pin is a multi-function output that can be configured as a general purpose
CMOS TRI-STATE output, push-pull analog lock detect output, open-drain analog lock detect output, digital
filtered lock detect output, or used to monitor the output of the various reference divider (R counter) or feedback
divider (N counter) circuits. The Ftest/LD control word is used to select the desired output function. When the
PLL is in powerdown mode, the Ftest/LD output is disabled and is in a high impedance state. A complete
programming description of the multi-function output is provided in MUX[3:0] - MULTIFUNCTION OUTPUT
SELECT (R3[23:22]:R0[23:22]).
Push-Pull Analog Lock Detect Output
An analog lock detect status generated from the phase detector is available on the Ftest/LD output pin if
selected. A push-pull configuration can be selected for the lock detect output signal. With this configuration, the
lock detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active
during a comparison cycle. Narrow low going pulses are observed when the charge pump turns on.
There are three separate push-pull analog lock detect signals that are routed to the multiplexer. Two of these
monitor the lock status of the individual synthesizers. The third detects the condition when both the RF and IF
synthesizers are in a locked state. External circuitry is required to provide a steady DC signal to indicate when
the PLL is in a locked state. Refer to MUX[3:0] - MULTIFUNCTION OUTPUT SELECT (R3[23:22]:R0[23:22]) for
details on how to program the different push-pull analog lock detect options.
Copyright © 2004, Texas Instruments Incorporated
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Product Folder Links: LMX2430 LMX2433 LMX2434