LMX2430_14 Datasheet, PDF (24/48 Pages) Texas Instruments – PLLatinum™ Dual High Frequency Synthesizer for RF Personal Communications

LMX2430, LMX2433, LMX2434
SNAS187B – MAY 2004 – REVISED MAY 2004
LMX243x FinRF Input Impedance Test Setup
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The block diagram above illustrates the setup required to measure the LMX243x device's RF input impedance.
The same setup is used for the LMX2430TM Evaluation Board. Measuring the device’s input impedance
facilitates the design of appropriate matching networks to match the PLL to the VCO, or in more critical
situations, to the characteristic impedance of the printed circuit board (PCB) trace, to prevent undesired
transmission line effects. The FinIF input impedance is evaluated in the same way.
Before the actual measurements are taken, the Network Analyzer needs to be calibrated, i.e. the error
coefficients need to be calculated. The Network Analyzer’s calibration standard is used to calculate these
coefficients. The calibration standard includes an open, short and a matched load. A 1-port calibration is
implemented here.
To calculate the coefficients, the PLL chip is first removed from the PCB. A piece of semi-rigid coaxial cable is
then soldered to the pad on the PCB which is equivalent to the FinRF pin on the PLL chip. Proper grounding
near the exposed tip of the semi-rigid coaxial cable is required for accurate results. Note that the DC blocking
capacitor is removed for this test. The Network Analyzer port is then connected to the other end of the semi-rigid
coaxial cable. In this way, the semi-rigid coaxial cable acts as a transmission line. This transmission line adds
electrical length and produces an offset from the reference plane of the Network Analyzer; therefore, it must be
included in the calibration. The desired operating frequency is then set. The typical frequency range selected for
the LMX243x device’s RF synthesizer is from 100 MHz to 6000 MHz.
The Network Analyzer calculates the calibration coefficients based on the measured S₁₁ parameters. With this all
done, calibration is now complete.
The PLL chip is then placed on the PCB. A power supply is then connected to Vcc. The EN, ENosc, and OSCin
pins are all tied to Vcc. Alternatively, the OSCin pin can be tied to ground. In this setup, the complementary input
(FinRF*) is AC coupled to ground. With the Network Analyzer still connected to the semi-rigid coaxial cable, the
measured FinRF impedance is displayed.
The OSCin input impedance is measured in the same way. The impedance is measured when the oscillator
buffer is powered up (ENosc is set HIGH) and when the oscillator buffer is powered down (ENosc pin is set
LOW).
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