LMC568 Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – Low Power Phase-Locked Loop

LMC568
SNAS559B – MAY 1999 – REVISED APRIL 2013
Notes to Typical Application
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SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at high supply voltages with high operating frequencies,
requiring C4 to be placed as close to possible to pin 4. Also, due to pin voltages tracking supply, a large C4 is
necessary for low frequency PSRR.
OSCILLATOR TIMING COMPONENTS
The voltage-controlled oscillator (VCO) on the LMC568 must be set up to run at twice the frequency of the input
signal. The components shown in the typical application are for F_osc = 200 kHz (100 kHz input frequency). For
operation at lower frequencies, increase the capacitor value; for higher frequencies proportionally reduce the
resistor values.
If low distortion is not a requirement, the series diode/resistor between pins 6 and 5 may be omitted. This will
reduce VCO supply dependence and increase V_out by approximately 2 dB with THD = 2% typical. The center
frequency as a function of Rt and Ct is given by:
(1)
To allow for I.C. and component value tolerences, the oscillator timing components will require a trim. This is
generally accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount
of initial frequency variation due to the LMC568 itself is given in the electrical specifications; the total trim range
must also accommodate the tolerances of Rt and Ct.
INPUT PIN
The input pin 3 is internally ground-referenced with a nominal 40 kΩ resistor. Signals that are centered on 0V
may be directly coupled to pin 3; however, any d.c. potential must be isolated via C3.
OUTPUT TAKEOFF
The output signal is taken off the loop filter at pin 2. Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL). The nominal pin 2 source resistance is 80 kΩ, requiring
the use of an external buffer transistor to drive nominal loads.
For small values of C2, the PLL will have a fast acquisition time and the pull-in range will be set by the built-in
VCO frequency stops, which also determine the largest detection bandwidth (LDBW). Increasing C2 results in
improved noise immunity at the expense of acquisition time, and the pull-in range will become narrower than the
LDBW. However, the maximum hold-in range will always equal the LDBW. The 2 kHz de-emphasis pole shown
may be modified or omitted as required by the application.
CARRIER DETECT
Pin 1 is the output of a negative-going amplitude detector which has a nominal 0 signal output of 7/9 V_s. The
output at pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input is
of sufficient amplitude to cause pin 1 to fall below 2/3 V_s. The carrier detect threshold is internally set to 26
mVrms typical on a 5V supply.
Capacitor C1 in conjunction with the nominal 40 kΩ pin 1 internal resistance forms the output filter. The size of
C1 is a tradeoff between slew rate and carrier ripple at the output comparator. Optional resistor R_H increases the
hysteresis in the pin 8 output for applications such as audio mute control. The minimum allowable value for R_H is
330 kΩ.
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