DAC5681Z Datasheet, PDF (4/61 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5681Z
SLLS865G – AUGUST 2007 – REVISED NOVEMBER 2015
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Pin Functions (continued)
PIN
NAME
NO.
D[15..0]N
8, 12, 14,
16, 18, 20,
22, 24, 28,
30, 32, 34,
36, 38, 41,
43
DCLKP
25
DCLKN
DVDD
EXTIO
EXTLO
GND
IOUTA1
26
10, 39, 50,
63
56
58
4, Thermal
Pad
52
IOUTA2
53
IOVDD
9
LPF
64
RESETB
49
SCLK
47
SDENB
48
SDIO
46
SDO
45
SYNCP
5
SYNCN
6
VFUSE
44
I/O
DESCRIPTION
LVDS negative input data bits 0 through 15. (See D[15:0]P description)
I
D15N is most significant data bit (MSB) – pin 8
D0N is least significant data bit (LSB) – pin 43
LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately
DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit.
I See DLL Operation. For proper external termination, connect a 100-Ω resistor across LVDS clock source
lines followed by series 0.01-μF capacitors connected to each of DCLKP and DCLKN pins (see Figure 65).
For best performance, the resistor and capacitors should be placed as close as possible to these pins.
I LVDS negative input clock. (See the DCLKP description)
I Digital supply voltage. (1.8 V)
Used as external reference input when internal reference is disabled ( that is, EXTLO connected to AVDD).
I/O Used as 1.2-V internal reference output when EXTLO = GND, requires a 0.1-μF decoupling capacitor to
AGND when used as reference output.
O Connect to GND for internal reference, or AVDD for external reference.
I
Pin 4 and the Thermal Pad located on the bottom of the VQFN package is ground for AVDD, DVDD and
IOVDD supplies.
DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current
O sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0-mA
current sink and the most positive voltage on the IOUTA1 pin.
DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described
O above. An input data value of 0x0000 results in a 0-mA sink and the most positive voltage on the IOUTA2
pin.
I Digital I/O supply voltage (3.3 V) for pins RESETB, SCLK, SDENB, SDIO, SDO.
I
PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both
PLL_bypass and PLL_sleep control bits for reduced power dissipation.
I Resets the chip when low. Internal pullup.
I Serial interface clock. Internal pulldown.
I Active low serial data enable, always an input to the DAC5681Z. Internal pullup.
I/O
Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the
SDIO pin is an input only. Internal pulldown.
Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state
O in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14
SDO_func_sel(2:0). Internal pulldown.
LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100-Ω termination resistor. By
I default, the SYNCP/N input must be logic 1 to enable a DAC analog output. See LVDS SYNCP/N
Operation.
I LVDS SYNC negative input data.
I
Digital supply voltage. (1.8 V) Connect to DVDD pins for normal operation. This supply pin is also used
for factory fuse programming.
4
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