DAC5681Z Datasheet, PDF (1/61 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
DAC5681Z
SLLS865G – AUGUST 2007 – REVISED NOVEMBER 2015
DAC5681Z 16-Bit, 1.0 GSPS 2x to 4x Interpolating Digital-To-Analog Converter (DAC)
1 Features
•1 16-Bit Digital-to-Analog Converter (DAC)
• 1.0 GSPS Update Rate
• 16-Bit Wideband Input LVDS Data Bus
– 8 Sample Input FIFO
• High Performance
– 73-dBc ACLR WCDMA TM1 at 180 MHz
• 2x to 32x Clock Multiplying PLL/VCO
• 2x or 4x Interpolation Filters
– Stopband Transition 0.4–0.6 Fdata
– Filters Configurable in Either Low-Pass or
High-Pass Mode
– Allows Selection of Higher Order Image
• On-Chip 1.2-V Reference
• 2 to 20-mA Differential Scalable Output
• 64-Pin 9-mm × 9-mm VQFN Package
2 Applications
• Cellular Base Stations
• Broadband Wireless Access (BWA)
• WiMAX 802.16
• Fixed Wireless Backhaul
• Cable Modem Termination System (CMTS)
3 Description
The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog
converter (DAC) with wideband LVDS data input,
integrated 2x to 4x interpolation filters, on-board clock
multiplier, and internal voltage reference. The
DAC5681Z offers superior linearity, noise, crosstalk,
and PLL phase noise performance.
The DAC5681Z integrates a wideband LVDS port
with on-chip termination. Full-rate input data can be
transferred to a single DAC channel, or half-rate and
1/4-rate input data can be interpolated by on-board
2x or 4x FIR filters. Each interpolation FIR is
configurable in either low-pass or high-pass mode,
allowing selection of a higher order output spectral
image. An on-chip delay lock loop (DLL) simplifies
LVDS interfacing by providing skew control for the
LVDS input data clock.
The DAC5681Z is characterized for operation over
the industrial temperature range of –40°C to 85°C
and is available in a 64-pin VQFN package. Other
members of the family include the dual-channel,
interpolating DAC5682Z and the single-channel, non-
interpolating DAC5681.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC5681z
VQFN (64)
9.00 mm × 9.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
CLKIN
CLKINC
DCLKP
DCLKN
D15P
D15N
D0P
D0N
SYNCP
SYNCN
PLL Bypass
Clock Multiplying
PLL 2x-32x
Delay Lock
Loop (DLL)
AB
PLL Control
DLL Control
Clock
Distribution
FDAC
FDAC/2
FDAC/4
PLL Enable
Sync Disable
Mode Control
16
(x2 Bypass)
(x1 Bypass)
x2
16
47t 76dB HBF
FIR0
16
SYNC=’0->1'
(transition)
TXEnable=’1'
SW_Sync
FIFO Sync Disable
x2
47t 76dB HBF
FIR1
Sync & Control
1.2V
Reference
EXTIO
EXTLO
BIASJ
13
2
16bit
DAC
4
IOUTA1
IOUTA2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.