DAC5681Z Datasheet, PDF (25/61 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)

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DAC5681Z
SLLS865G – AUGUST 2007 – REVISED NOVEMBER 2015
Agilent 81205A
ParBERT
Pattern
Memory
Optional
Divider
Agilent 8133A
Pulse Generator
DAC5681ZEVM SMA Adapter Board
D15
P
N
D0
P
N
SYNC P
N
DCLK
P
N
36 each
SMA-SMA cables
HP8665B
Synthesized
Signal
Generator
100
100
100
100
DAC5681Z DAC
DAC
3.3 V
100
3.3 V
100
3.3 V
DLL
opt.
PLL
CDCM7005
Opt.
Clock
Divider
Loop
Filter
100
DAC5681ZEVM
Figure 34. DAC5681Z Test Configuration for Normal Clock Mode
Rohde &
Schwartz
FSU
Spectrum
Analyzer
7.3.11 CMOS Digital Inputs
Figure 35 shows a schematic of the equivalent CMOS digital inputs of the DAC5681Z. SDIO and SCLK have
pulldown resistors while RESETB and SDENB have pullup resistors internal the DAC5681Z. See Specifications.
The pullup and pulldown circuitry is approximately equivalent to 100 kΩ.
IOVDD
IOVDD
SDIO
SCLK
internal
digital in
RESETB
SDENB
internal
digital in
IOGND
Figure 35. CMOS/TTL Digital Equivalent Input
IOGND
7.3.12 Digital Self Test Mode
The DAC5681Z has a Digital Self Test (SLFTST) mode to designed to enable board level testing without
requiring specific input data test patterns. The SLFTST mode is enabled via the CONFIG1 SLFTST_ena bit and
results are only valid when CONFIG3 SLFTST_err_mask bit is cleared. An internal Linear Feedback Shift
Register (LFSR) is used to generate the input test patterns for the full test cycle while a checksum result is
computed on the digital signal chain outputs. The LVDS input data bus is ignored in SLFTST mode. After the test
cycle completes, if the checksum result does not match a hardwired comparison value, the STATUS4
SLFTST_err bit is set and will remain set until cleared by writing a 0 to the SLFTST_err bit. A full self test cycle
requires no more than 400,000 CLKIN/C clock cycles to complete and will automatically repeat until the
SLFTEST_ena bit is cleared.
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