ADC12DL080_14 Datasheet, PDF(4/35 Page) Texas Instruments – Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

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ADC12DL080_14 Datasheet, PDF (4/35 Pages) Texas Instruments – Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

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ADC12DL080

SNAS345 â FEBRUARY 2006

Pin No.

Symbol

VINA+

VINB+

VINAâ

VINBâ

VREF

REFSEL/DCS

DIGITAL I/O

VRPA

VRPB

VRMA

VRMB

VRNA

VRNB

Equivalent Circuit

Description

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AGND

Differential analog input pins. With a 1.0V reference voltage the

differential full-scale input signal level is 2.0 VP-P with each input pin

voltage centered on a common mode voltage, VCM. The negative

input pins may be connected to VCM for single-ended operation, but

a differential input signal is required for best performance.

AGND

(1)

This pin is used in conjunction with REFSEL/DCS (pin 11) to select

the internal 1.0V reference, or as the external reference input.

If VREF is tied HIGH, the internal 1.0V reference is selected.

REFSEL/DCS must be LOW or tied to VRMA or VRMB.

If a voltage in the range of 0.8V to 1.2V is applied to this pin, that

voltage is used as the reference. VREF should be bypassed to AGND

with a 0.1 ÂµF low ESL capacitor when an external reference is used.

The nominal external reference voltage is 1.0V but values in the

range of 0.8V to 1.2V may be used. REFSEL/DCS must be HIGH or

REFSEL/DCStied to VRMA or VRMB.

See Table 4 in for more information.

This pin is used in conjunction with VREF (pin 7) to select the

reference source and turn the Duty Cycle Stabilizer (DCS) on or off.

When REFSEL/DCS is LOW and VREF is HIGH, the internal 1.0V

(2)

reference is selected and DCS is On.

When REFSEL/DCS is HIGH, an external reference voltage in the

range of 0.8V to 1.2V should be applied to the VREF input. DCS is

On.

With this pin connected to VRMA or VRMB, DCS is Off.

See Table 4 in REFSEL/DCS for more information.

AGND

These are reference bypass pins. These pins should each be

bypassed to ground with a 0.1 ÂµF capacitor. A 10 ÂµF capacitor

should be placed between the VRPA and VRNA pins and between the

VRPB and VRNB pins.

These pins should not be loaded.

(3)

CLK

OF/DOEN

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AGND

DGND

Digital clock input. The range of frequencies for this input is as

specified in the electrical tables with guaranteed performance at 80

MHz. The inputs are sampled on the rising edge.

AGND

(4)

OF/DOEN selects the output format (OF) or enables the DRDY

output (DOEN). The state of this pin also controls the function of pins

22 and 41.

When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41

is used as the DRDY output strobe, and pin 22 is used to select the

output format. Output Enable for channels A and B are not available

in this mode.

When OF/DOEN is LOW, the output data format is offset binary.

With OF/DOEN tied HIGH, the output format is 2's complement.

See Table 5 in OF/DOEN, OEA/OF, and OEB/DRDY for more

information.

(5)

Product Folder Links: ADC12DL080

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