ADC12DL080_14 Datasheet, PDF (26/35 Pages) Texas Instruments – Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

ADC12DL080
SNAS345 – FEBRUARY 2006
www.ti.com
The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and
14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry
before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down
mode, but can result in a reduction in SNR, SINAD and ENOB performance.
OUTPUTS
The ADC12DL080 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at
these outputs while the OE and PD pins are low. Be very careful when driving a high capacitance bus. The more
capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows
through V_DR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into
the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and
careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified
10 pF/pin will cause t_OD to increase, making it difficult to properly latch the ADC output data. The result could be
an apparent reduction in dynamic performance.
To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by
connecting buffers (74LVTH162374, for example) between the ADC outputs and any other circuitry. Only one
driven input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the
digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit
the output currents, which could otherwise result in performance degradation. See Figure 5.
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