ADC12DL080_14 Datasheet, PDF (25/35 Pages) Texas Instruments – Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

ADC12DL080
www.ti.com
SNAS345 – FEBRUARY 2006
where t_PD is the signal propagation rate down the clock line, "L" is the line length and Z_O is the characteristic
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it
as seen from the clock source. Typical t_PD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of
"L" and t_PD should be the same (inches or centimeters).
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC12DL080 has a Duty Cycle Stabilizer which can be enabled using the
REFSEL/DCS pin. It is designed to maintain performance over a clock duty cycle range of 30% to 70% at 80
MSPS.
REFSEL/DCS
This pin is used in conjunction with V_REF (pin 7) to select the reference source and turn the Duty Cycle Stabilizer
(DCS) on or off.
When REFSEL/DCS is LOW and V_REF is HIGH, the internal 1.0V reference is selected and DCS is On.
When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the
VREF input. DCS is On.
With this pin connected to V_RMA or V_RMB, DCS is Off.
When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to
70% and generate a stable internal clock, improving the performance of the part.
REFSEL/DCS (pin 11)
Logic LOW
Logic High
V_RMA or V_RMB
V_RMA or V_RMB
Table 4. V_REF, REFSEL/DCS Pin Functions
V_REF (pin 7)
Logic HIGH
Reference
Internal 1.0 V
0.8 to 1.2V
External
Logic High
Internal 1.0V
0.8 to 1.2V
External
DCS
ON
ON
OFF
OFF
OF/DOEN, OEA/OF, and OEB/DRDY
OF/DOEN (pin 21) selects the output format (OF) or enables the DRDY output (DOEN). The state of this pin also
controls the function of pins 22 (OEA/OF) and 41 (OEB/DRDY).
When OF/DOEN is tied to V_RMA or V_RMB, DRDY is enabled. Pin 41 is used as the DRDY output strobe, and pin
22 is used to select the output format. Output Enable for channels A and B are not available in this mode.
When OF/DOEN is LOW, the output data format is offset binary. With OF/DOEN tied HIGH, the output format is
2's complement.
The following table describes the function of these pins.
Pin 21 State
V_RMA or V_RMB
Logic LOW
Logic HIGH
Table 5. OF/DOEN, OEA/OF, OEB/DRDY Pin Functions
Pin 21 Function
DRDY output is enabled
Output Format = Offset Binary
Output Format = 2's Complement
Pin 22 Function
Output Format
LOW = Offset Binary
HIGH = 2's Complement
Output Enable for Channel A
LOW = outputs are enabled
HIGH = outputs are in high
impedance state
Pin 41 Function
DRDY Output
Output Enable for Channel B
LOW = outputs are enabled
HIGH = outputs are in high
impedance state
PD
The PD pin, when high, holds the ADC12DL080 in a power-down mode to conserve power when the converter is
not being used. The output data pins are undefined and the data in the pipeline is corrupted while in the power
down mode.
Copyright © 2006, Texas Instruments Incorporated
Product Folder Links: ADC12DL080
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