SM32C6416T-EP Datasheet, PDF (39/130 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SM32C6416T-EP
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006
Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AC7
I
Device reset
NMI
B4
I
IPD Nonmaskable interrupt, edge-driven (rising edge)
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
GP15/PRST§
GP14/PCLK§
GP13/PINTA§
GP12/PGNT§
GP11/PREQ§
GP10/PCBE3§
GP9/PIDSEL§
AF4
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The
AD5
default after reset setting is GPIO enabled as input-only.
I/O/Z IPU • When these pins function as External Interrupts [by selecting the corresponding interrupt
AE5
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
AF5
independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
G3
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
F2
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
J3
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
F1
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
L2
I/O/Z
M3
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
GP3
AC6
IPD GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only.
GP0
GPIO 0 pin.
AF6
IPD
The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only)
[default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT)
signal (output only).
CLKS2/GP8§
AE4
I/O/Z
IPD
McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be pro-
grammed as a GPIO 8 pin (I/O/Z).
CLKOUT6/GP2§
AD6
I/O/Z
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
CLKOUT4/GP1§
AE6
I/O/Z
IPD
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI)
PCI_EN
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
AA4
I
IPD PCI peripherals. This pin works in conjunction with the MCBSP2_EN pin to enable/disable
other peripherals (for more details, see the Device Configurations section of this data sheet).
HINT/PFRAME§
R4
I/O/Z
Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)
HCNTL1/
PDEVSEL§
R1
I/O/Z
Host control − selects between control, address, or data registers (I) [default] or PCI device
select (I/O/Z).
HCNTL0/
PSTOP§
T4
I/O/Z
Host control − selects between control, address, or data registers (I) [default] or PCI stop
(I/O/Z)
HHWIL/PTRDY§
R3
I/O/Z
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
HR/W/PCBE2§
P1
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
§ _{These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.}
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