SM32C6416T-EP Datasheet, PDF (117/130 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SM32C6416T-EP
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 11b, CLKXP = 0^†‡ (see Figure 54)
NO.
PARAMETER
1 th(CKXL-FXL)
2 td(FXL-CKXH)
Hold time, FSX low after CLKX low#
Delay time, FSX low to CLKX high||
3 td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
−600§, −720§
−850, −1G
MASTER¶
SLAVE
MIN MAX
MIN
MAX
L−2 L+3
T−2 T+3
−2
4 12P + 2.8 20P + 17
UNIT
ns
ns
ns
−2
4 12P + 3 20P + 17 ns
7 td(FXL-DXV)
Delay time, FSX low to DX valid
H − 2 H + 4 8P + 2 16P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.}
‡ _{For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{Product Preview device}
¶ _{S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)}
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) x S
H = CLKX high pulse width = (CLKGDV/2 + 1) x S if CLKGDV is even
= (CLKGDV + 1)/2 x S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) x S if CLKGDV is even
= (CLKGDV + 1)/2 x S if CLKGDV is odd or zero
# _{FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
|| _{FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock}
(CLKX).
CLKX
FSX
DX
DR
1
6
Bit 0
Bit 0
2
7
3
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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117