TM4C123GH6ZRB Datasheet, PDF (373/1471 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C123GH6ZRB Microcontroller
Register 79: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock
Gating Control (SCGCUART), offset 0x718
The SCGCUART register provides software the capability to enable and disable the UART modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the UART modules. To support
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as UART0), the write
causes proper operation, but the value of that bit is not reflected in the SCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART)
Base 0x400F.E000
Offset 0x718
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
S7
S6
S5
S4
S3
S2
S1
S0
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
Name
reserved
S7
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Module 7 Sleep Mode Clock Gating Control
Value Description
0 UART module 7 is disabled.
1 Enable and provide a clock to UART module 7 in sleep mode.
6
S6
RW
0
UART Module 6 Sleep Mode Clock Gating Control
Value Description
0 UART module 6 is disabled.
1 Enable and provide a clock to UART module 6 in sleep mode.
June 12, 2014
373
Texas Instruments-Production Data