TM4C123GH6ZRB Datasheet, PDF (288/1471 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 25: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC
This register provides status information on the Sleep and Deep-Sleep power modes as well as
some real time status that can be viewed by a debugger or the core if it is running. These events
do not trigger an interrupt and are meant to provide information that can help tune software for power
management. The status register gets written at the beginning of every Dynamic Power Management
event request with the results of any error checking. There is no mechanism to clear the bits; they
are overwritten on the next event. The LDOUA, FLASHLP, LOWPWR, PRACT bits provide real time
data and there are no events to register that information.
Sleep / Deep-Sleep Power Mode Status (SDPMST)
Base 0x400F.E000
Offset 0x1CC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
16
LDOUA FLASHLP LOWPWR PRACT
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
PPDW LMAXERR reserved LSMINERR LDMINERR PPDERR FPDERR SPDERR
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
Bit/Field
31:20
19
Name
reserved
LDOUA
Type
RO
RO
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LDO Update Active
Value Description
0 The LDO voltage level is not changing.
1 The LDO voltage level is changing.
18
FLASHLP
RO
0
Flash Memory in Low Power State
Value Description
0 The Flash memory is currently in the active state.
1 The Flash memory is currently in the low power state as
programmed in the SLPPWRCFG or DSLPPWRCFG register.
17
LOWPWR
RO
0
Sleep or Deep-Sleep Mode
Value Description
0 The microcontroller is currently in Run mode.
1 The microcontroller is currently in Sleep or Deep-Sleep mode
and is waiting for an interrupt or is in the process of powering
up. The status of this bit is not affected by the power state of
the Flash memory or SRAM.
288
June 12, 2014
Texas Instruments-Production Data