AM5718 Datasheet, PDF (372/388 Pages) Texas Instruments – AM571x Sitara™ Processors Silicon Revision 2.0

AM5718, AM5716
SPRS957A – MARCH 2016 – REVISED JUNE 2016
8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-24 and Figure 8-25 show the DQS and DQ/DM routing.
DQSn+
DQSn-
Routed Differentially
DQS
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n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
Figure 8-24. DQS Routing With Any Number of Allowed DDR3 Devices
DQ and DM
Dn
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
Figure 8-25. DQ/DM Routing With Any Number of Allowed DDR3 Devices
8.2.2.17 Routing Specification
8.2.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
372 Applications, Implementation, and Layout
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