AM5718 Datasheet, PDF (256/388 Pages) Texas Instruments – AM571x Sitara™ Processors Silicon Revision 2.0

AM5718, AM5716
SPRS957A – MARCH 2016 – REVISED JUNE 2016
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The MCSPI is a master/slave synchronous serial bus. There are four separate MCSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The MCSPI modules include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of SPI word lengths, ranging from 4 to 32 bits
• Up to four master channels, or single channel in slave mode
• Master multichannel mode:
– Full duplex/half duplex
– Transmit-only/receive-only/transmit-and-receive modes
– Flexible input/output (I/O) port controls per channel
– Programmable clock granularity
– SPI configuration per channel. This means, clock definition, polarity enabling and word width
• Power management through wake-up capabilities
• Programmable timing control between chip select and external clock generation
• Built-in FIFO available for a single channel.
• Each SPI module supports multiply chip select pins spim_cs[i], where i = 1 to 4.
NOTE
For more information, see the Serial Communication Interface section of the device TRM.
NOTE
The MCSPIm module (m = 1 to 4) is also referred to as SPIm.
CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in
Table 7-41.
Table 7-39, Figure 7-33 and Figure 7-34 present Timing Requirements for McSPI - Master Mode.
Table 7-39. Timing Requirements for SPI - Master Mode ⁽¹⁾⁽⁸⁾
NO.
SM1
PARAMETER
t_c(SPICLK)
SM2 t_w(SPICLKL)
SM3 t_w(SPICLKH)
SM4
SM5
SM6
t_{su(MISO-SPICLK)}
t_{h(SPICLK-MISO)}
t_{d(SPICLK-SIMO)}
SM7 t_d(CS-SIMO)
DESCRIPTION
Cycle time, spi_sclk ^{(1) (2)}
Typical Pulse duration, spi_sclk low ⁽¹⁾
Typical Pulse duration, spi_sclk high ⁽¹⁾
Setup time, spi_d[x] valid before spi_sclk active edge ⁽¹⁾
Hold time, spi_d[x] valid after spi_sclk active edge ⁽¹⁾
Delay time, spi_sclk active edge to spi_d[x] transition ⁽¹⁾
Delay time, spi_cs[x] active edge to spi_d[x] transition
MODE
SPI1/2/3/
4
MIN
20.8 ⁽³⁾
0.5*P-1
(4)
0.5*P-1
(4)
SPI1/2/4
SPI3
2.29
3.2
-3.57
-3.57
MAX
3.57
3.57
3.57
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
256 Timing Requirements and Switching Characteristics
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