LMK04906 Datasheet, PDF (37/117 Pages) Texas Instruments – Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs

LMK04906
18.5.1 Holdover Frequency Accuracy and DAC Performance
When in holdover mode PLL1 will run in open loop and the DAC will set the CPout1 voltage. If Fixed CPout1 mode is used, then
the output of the DAC will be a voltage dependant upon the MAN_DAC register. If Tracked CPout1 mode is used, then the output
of the DAC will be the voltage at the CPout1 pin before holdover mode was entered. When using Tracked mode and EN_MAN_DAC
= 1, during holdover the DAC value is loaded with the programmed value in MAN_DAC, not the tracked value.
When in Tracked CPout1 mode the DAC has a worst case tracking error of ±2 LSBs once PLL1 tuning voltage is acquired. The
step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode caused by the DAC tracking accuracy
is ±6.4 mV * Kv. Where Kv is the tuning sensitivity of the VCXO in use. Therefore the accuracy of the system when in holdover
mode in ppm is:
30179159
Example: consider a system with a 19.2 MHz clock input, a 153.6 MHz VCXO with a Kv of 17 kHz/V. The accuracy of the system
in holdover in ppm is:
±0.71 ppm = ±6.4 mV * 17 kHz/V * 1e6 / 153.6 MHz
It is important to account for this frequency error when determining the allowable frequency error window to cause holdover mode
to exit.
18.5.2 Holdover Mode - Automatic Exit of Holdover
The LMK04906 device can be programmed to automatically exit holdover mode when the accuracy of the frequency on the active
clock input achieves a specified accuracy. The programmable variables include PLL1_WND_SIZE and DLD_HOLD_CNT.
See Section 20.6 DIGITAL LOCK DETECT FREQUENCY ACCURACY to calculate the register values to cause holdover to au-
tomatically exit upon reference signal recovery to within a user specified ppm error of the holdover frequency.
It is possible for the time to exit holdover to vary because the condition for automatic holdover exit is for the reference and feedback
signals to have a time/phase error less than a programmable value. Because it is possible for two clock signals to be very close in
frequency but not close in phase, it may take a long time for the phases of the clocks to align themselves within the allowable time/
phase error before holdover exits.
18.6 PLLs
18.6.1 PLL1
PLL1's maximum phase detector frequency (f_PD1) is 40 MHz. Since a narrow loop bandwidth should be used for PLL1, the need
to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary. The maximum values for the PLL1
R and N dividers is 16,383. Charge pump current ranges from 100 to 1600 µA. PLL1 N divider may be driven by OSCin port at the
OSCout0_MUX output (default) or by internal or external feedback as selected by Feedback Mux in 0-delay mode.
Low charge pump currents and phase detector frequencies aid design of low loop bandwidth loop filters with reasonably sized
components to allow the VCXO or PLL2 to dominate phase noise inside of PLL2 loop bandwidth. High charge pump currents may
be used by PLL1 when using VCXOs with leaky tuning voltage inputs to improve system performance.
18.6.2 PLL2
PLL2's maximum phase detector frequency (f_PD2) is 155 MHz. Operating at highest possible phase detector rate will ensure low
in-band phase noise for PLL2 which in turn produces lower total jitter. The in-band phase noise from the reference input and PLL
is proportional to N². The maximum value for the PLL2 R divider is 4,095. The maximum value for the PLL2 N divider is 262,143.
The N2 Prescaler in the total N feedback path can be programmed for values 2 to 8 (all divides even and odd). Charge pump current
ranges from 100 to 3200 µA.
High charge pump currents help to widen the PLL2 loop bandwidth to optimize PLL2 performance.
18.6.2.1 PLL2 FREQUENCY DOUBLER
The PLL2 reference input at the OSCin port may be routed through a frequency doubler before the PLL2 R Divider. The frequency
doubler feature allows the phase comparison frequency to be increased when a relatively low frequency oscillator is driving the
OSCin port. By doubling the PLL2 phase detector frequency, the in-band PLL2 noise is reduced by about 3 dB.
For applications in which the OSCin frequency and PLL2 phase detector frequency are equal, the best PLL2 in-band noise can be
achieved when the doubler is enabled (EN_PLL2_REF_2X = 1) and the PLL2 R divide value is 2. Do not use doubler disabled
(EN_PLL2_REF_2X = 0) and PLL2 R divide value of 1.
When using the doubler take care to use the PLL2 R Divider to reduce the phase detector frequency to the limit of the PLL2 maximum
phase detector frequency.
Copyright © 1999-2012, Texas Instruments Incorporated
37