LMK04906 Datasheet, PDF (1/117 Pages) Texas Instruments – Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs

LMK04906
Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable
Outputs
1.0 General Description
The LMK04906 is the industry's highest performance clock
jitter attenuator with superior clock jitter cleaning, generation,
and distribution with advanced features to meet high perfor-
mance timing application needs.
The LMK04906 accepts 3 clock input ranging from 1 kHz to
750 MHz and generates 6 unique clock output frequencies
ranging from 2.26 MHz to 2.6 GHz. The LMK04906 can also
buffer a crystal or VCXO to generate a 7^th unique clock fre-
quency.
The device provides virtually all frequency translation combi-
nation required for SONET, Ethernet, Fibre Channel and mul-
ti-mode Wireless Base Stations.
The LMK04906 input clock frequency and clock multiplication
ratio are programmable through a SPI interface.
Device
LMK04906
VCO Frequency
2370 to 2600 MHz
2.0 Target Applications
• 10G/40G/100G OTN line cards
• SONET/SDH OC-48/STM-16 and OC-192/STM-64line
cards
• GbE/10GbE, 1/2/4/8/10GFC line cards
• ITU G.709 and custom FEC line cards
• Synchronous Ethernet
• Optical modules
• DSLAM/MSANs
• Test and measurement
• Broadcast video
• Wireless basestations
• Data converter clocking
• Microwave ODU and IDUs for Wireless Backhaul
3.0 Features
● ^{Ultra-Low RMS Jitter Performance}
— 100 fs RMS jitter (12 kHz to 20 MHz)
— 123 fs RMS jitter (100 Hz to 20 MHz)
● ^{Dual Loop PLLatinum™ PLL Architecture}
— PLL1
● ^{Integrated Low-Noise Crystal Oscillator Circuit}
● ^{Holdover mode when input clocks are lost}
— Automatic or manual triggering/recovery
— PLL2
● ^{Normalized [1 Hz] PLL noise floor of -227 dBc/Hz}
● ^{Phase detector rate up to 155 MHz}
● ^{OSCin frequency-doubler}
● ^{Integrated Low-Noise VCO}
● ^{3 redundant input clocks with LOS}
— Automatic and manual switch-over modes
● ^{50% duty cycle output divides, 1 to 1045 (even and odd)}
● ^{LVPECL, LVDS, or LVCMOS programmable outputs}
● ^{Precision digital delay, fixed or dynamically adjustable}
● ^{25 ps step analog delay control.}
● ^{6 differential outputs. Up to 12 single ended.}
— Up to 5 VCXO/Crystal buffered outputs
● ^{Clock rates of up to 2600 MHz}
● ^{0-delay mode}
● ^{Three default clock outputs at power up}
● ^{Multi-mode: Dual PLL, single PLL, and clock distribution}
● ^{Industrial Temperature Range: -40 to 85 °C}
● ^{3.15 V to 3.45 V operation}
● ^{Package: 64-pin QFN (9.0 x 9.0 x 0.8 mm)}
System Application Diagram
30179139
PLLatinum™ is a trademark of National Semiconductor Corporation.
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
301791 SNAS589B
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