BQ27742-G1 Datasheet, PDF (35/46 Pages) Texas Instruments – Single-Cell Li-Ion Battery Fuel Gauge with Programmable Hardware Protection

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bq27742-G1
SLUSBV9C – MARCH 2014 – REVISED FEBRUARY 2016
8.2.3.11 NFET Selection
The choice in NFETs for a single-cell battery pack design will depend on a variety of factors including package
type, size, and device cost as well as performance metrics such as drain-to-source resistance (r_DS(on)), gate
capacitance, maximum current and power handling, and similar. At a bare minimum, it is recommended that the
selected FETs have a drain-to-source voltage (V_DS) and gate-to-source (V_GS) voltage tolerance of 12 V. Some
FETs can are designed to handle as much as 24 V between the drain and source terminals and this would
provide an increased safety margin for the pack design. Further, the DC current rating should be high enough to
safely handle sustained current in charge or discharge direction just below the maximum threshold tolerances of
the configured OCC and OCD protections and the lowest possible sense resistance value based on tolerance
and TCR considerations, or vice-versa. This ensures that there is sufficient power dissipation margin given a
worst case scenario for the fault detections. In addition, striving for minimal FET resistance at the expected gate
bias as well as lowest gate capacitance will help reduce conduction losses and increase power efficiency as well
as achieve faster turn-on and turn-off times for the FETs. Many of these FETs are now offered as dual, back-
back NFETs in wafer-chip scale (WCSP) packaging, decreasing both BOM count and shrinking necessary board
real estate to accommodate the components. Last, one should always refer to the safe operating area (SOA)
curves of the target FETs to ensure that the boundaries are never violated based on all possible load conditions
in the end application. The CSD83325L is an excellent example of a FET solution that meets all of the
aforementioned criteria, offering r_DS(on) of 10.3 mΩ and V_DS of 12 V with back-to-back NFETs in a chip-scale
package, a perfect fit for battery pack designs.
8.2.3.12 Additional ESD Protection Components
The additional capacitors placed across the CHG and DSF FET source pins as well as between PACK+ and
ground help to bolster and greatly improve the ESD robustness of the pack design. The former components
shunt damaging transients around the FETs and the latter components attempt to bypass such pulses to PACK–
before they couple further into the battery pack PCB. Two series capacitors are used for each of these protection
areas to prevent a battery short in the event of a single capacitor failure.
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