TMS320F28030_14 Datasheet, PDF (34/158 Pages) Texas Instruments – Piccolo™ Microcontrollers

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J – APRIL 2009 – REVISED OCTOBER 2013
www.ti.com
3.2.12 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be
enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero
when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept
inputs from GPIO0–GPIO31 pins.
3.2.13 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling
ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating
frequency if lower power operation is desired. Refer to Section 6, Electrical Specifications, for timing
details. The PLL block can be set in bypass mode.
3.2.14 Watchdog
Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a
certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog
can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
3.2.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I²C) can be scaled
relative to the CPU clock.
3.2.16 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
This mode basically shuts down the device and places it in the lowest possible power
consumption mode. If the internal zero-pin oscillators are used as the clock source,
the HALT mode turns them off, by default. To keep these oscillators from shutting
down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip
crystal oscillator is used as the clock source, it is shut down in this mode. A reset or
an external signal (through a GPIO pin) or the CPU-watchdog can wake the device
from this mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put
the device into HALT or STANDBY.
34
Functional Overview
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