TMS320F28030_14 Datasheet, PDF (135/158 Pages) Texas Instruments – Piccolo™ Microcontrollers

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584J – APRIL 2009 – REVISED OCTOBER 2013
Table 6-35. SPI Slave Mode External Timing (Clock Phase = 1)^(1)(2)(3)(4)
NO.
MIN
MAX
12 t_c(SPC)S
13 t_w(SPCH)S
t_w(SPCL)S
14 t_w(SPCL)S
t_w(SPCH)S
17 t_{su(SOMI-SPCH)S}
t_{su(SOMI-SPCL)S}
18 t_{v(SPCL-SOMI)S}
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
8t_c(LCO)
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.125t_c(SPC)S
0.125t_c(SPC)S
0.75t_c(SPC)S
0.5t_c(SPC)S
0.5t_{c(SPC) S}
0.5t_{c(SPC) S}
0.5t_c(SPC)S
t_{v(SPCH-SOMI)S}
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
0.75t_{c(SPC) S}
21 t_{su(SIMO-SPCH)S}
t_{su(SIMO-SPCL)S}
22 t_{v(SPCH-SIMO)S}
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
26
26
0.5t_c(SPC)S – 10
t_{v(SPCL-SIMO)S}
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5t_c(SPC)S – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
UNIT
ns
ns
ns
ns
ns
ns
ns
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISOMI
12
13
14
17
18
SPISOMI data is valid
Data Valid
SPISIMO
21
22
SPISIMO data
must be valid
SPISTE^(A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC) before the valid SPI clock edge and
remain low for at least 0.5t_c(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-24. SPI Slave Mode External Timing (Clock Phase = 1)
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Electrical Specifications 135
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