TMS320F28030_14 Datasheet, PDF (133/158 Pages) Texas Instruments – Piccolo™ Microcontrollers

www.ti.com
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J – APRIL 2009 – REVISED OCTOBER 2013
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
6
7
Master out data Is valid
10
11
Master in data
must be valid
3
Data Valid
SPISTE^(A)
A. In the master mode, SPISTE goes active 0.5t_c(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5t_c(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-22. SPI Master Mode External Timing (Clock Phase = 1)
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
Electrical Specifications 133