OPA191_017 Datasheet, PDF (34/51 Pages) Texas Instruments – 36-V, Low Power, Precision, CMOS, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp

OPA191, OPA2191, OPA4191
SBOS701A – DECEMEBER 2015 – REVISED APRIL 2016
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Typical Applications (continued)
primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system
are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,
carefully design each analog circuit block based on the ADC performance specifications in order to achieve the
fastest settling at 16-bit resolution and lowest distortion system. Figure 64 includes the most important
specifications for each individual analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for an extremely-low-impedance input-filter design for the mux. This
understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system
settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to
level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability.
Then, the next step is to design a digital interface to switch the mux input channels with minimum delay. The final
design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference
voltage with low offset, drift, and noise contributions.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
9.2.3 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx191 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.Figure 65 shows the OPA191 in a slew-rate limit design.
Op Amp Gain Stage
VCC
-
VIN
OPA191
+
VEE
Slew Rate Limiter
R2
C1
R1
VCC
-
OPA191
+
VEE
VOUT
RL
Figure 65. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
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