LM3697_15 Datasheet, PDF (34/43 Pages) Texas Instruments – High-Efficiency Three-String White LED Driver

LM3697
SNOSCS2C – NOVEMBER 2013 – REVISED OCTOBER 2015
www.ti.com
Layout Guidelines (continued)
3. Inductor
– SW Node PCB capacitance to other traces
4. Input Capacitor
– CIN+ to IN terminal
10.1.1 Boost Output Capacitor Placement
Because the output capacitor is in the path of the inductor current discharge path it detects a high-current step
from 0 to I_PEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series
path from the cathode of the diode through COUT and back into the LM3697 device's GND pin contributes to
voltage spikes (V_SPIKE = L_{P_} × di/dt) at SW and OUT. These spikes can potentially over-voltage the SW pin, or
feed through to GND. To avoid this, COUT+ must be connected as close as possible to the cathode of the
Schottky diode, and COUT− must be connected as close as possible to the LM3697 device's GND bump. The
best placement for COUT is on the same layer as the LM3697 in order to avoid any vias that can add excessive
series inductance.
10.1.2 Schottky Diode Placement
In the LM3697 device’s boost circuit the Schottky diode is in the path of the inductor current discharge. As a
result the Schottky diode sees a high-current step from 0 to I_PEAK each time the switch turns off and the diode
turns on. Any inductance in series with the diode causes a voltage spike (V_SPIKE = L_{P_} × di/dt) at SW and OUT.
This can potentially over-voltage the SW pin, or feed through to V_OUT and through the output capacitor and into
GND. Connecting the anode of the diode as close as possible to the SW pin and the cathode of the diode as
close as possible to COUT and reduces the inductance (L_{P_}) and minimize these voltage spikes.
10.1.3 Inductor Placement
The node where the inductor connects to the LM3697 device’s SW pin has 2 issues. First, a large switched
voltage (0 to V_OUT + V_{F_SCHOTTKY}) appears on this node every switching cycle. This switched voltage can be
capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces
connecting the input supply to the inductor and connecting the inductor to the SW pin. Any resistance in this path
can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range.
To reduce the capacitive coupling of the signal on SW into nearby traces, the SW pin-to-inductor connection
must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high-
impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not
directly adjacent or beneath. This is especially true for traces such as SCL, SDA, HWEN, and PWM. A GND
plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.
Lastly, limit the trace resistance of the VIN-to-inductor connection and from the inductor to SW connection, by
use of short, wide traces.
10.1.4 Boost Input Capacitor Placement
For the LM3697 device’s boost converter, the input capacitor filters the inductor current ripple and the internal
MOSFET driver currents during turnon of the internal power switch. The driver current requirement can range
from 50 mA at 2.7 V to over 200 mA at 5.5 V with fast durations of approximately 10 ns to 20 ns. This appears
as high di/dt current pulses coming from the input capacitor each time the switch turns on. Close placement of
the input capacitor to the IN pin and to the GND in is critical because any series inductance between IN and
CIN+ or CIN− and GND can create voltage spikes that could appear on the VIN supply line and in the GND
plane.
34
Submit Documentation Feedback
Product Folder Links: LM3697
Copyright © 2013–2015, Texas Instruments Incorporated