LM3697_15 Datasheet, PDF (16/43 Pages) Texas Instruments – High-Efficiency Three-String White LED Driver

LM3697
SNOSCS2C – NOVEMBER 2013 – REVISED OCTOBER 2015
Device Functional Modes (continued)
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SDA
SCL
S
P
Start Condition
Stop Condition
Figure 12. Start And Stop Sequences
7.4.3.2 I²C-Compatible Address
The chip address for the LM3697 is 0110110 (36h). After the START condition, the I²C master sends the 7-bit
chip address followed by an eighth read or write bit (R/W). R/W= 0 indicates a WRITE and R/W = 1 indicates a
READ. The second byte following the chip address selects the register address to which the data is written. The
third byte contains the data for the selected register.
7.4.3.3 Transferring Data
Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte
of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is
generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3697 pulls down
SDA during the 9th clock pulse signifying an acknowledge. An acknowledge is generated after each byte has
been received.
Table 2 lists the available registers within the LM3697.
7.4.3.4 High-Speed Mode
The LM3697 supports only Standard and Fast mode I²C operation. High Speed mode is not supported. If the
LM3697 is connected to a I²C-bus with a HS-mode device a dummy I²C cycle is required after the HS-mode
command is complete. The dummy cycle can be a read or write to any I²C slave address.
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