AM5718_17 Datasheet, PDF (331/396 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

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AM5718, AM5716
SPRS957D – MARCH 2016 – REVISED JANUARY 2017
7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
Table 7-135. PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
NO. PARAMETER
DESCRIPTION
MIN
1
tw(SDx_CLK)
Pulse width, SDx_CLK
20
2
tsu(SDx_D-SDx_CLK) Setup time, SDx_D valid before SDx_CLK active edge
10
3
th(SDx_CLK-SDx_D) Hold time, SDx_D valid before SDx_CLK active edge
5
MAX
UNIT
ns
ns
ns
1
SDx_CLK
SDx_D
2
3
SPRS91x_TIMING_PRU_07
Figure 7-98. PRU-ICSS PRU SD_CLK Falling Active Edge
1
SDx_CLK
SDx_D
2
3
SPRS91x_TIMING_PRU_08
Figure 7-99. PRU-ICSS PRU SD_CLK Rising Active Edge
Table 7-136. PRU-ICSS PRU Timing Requirements - EnDAT Mode
NO. PARAMETER
DESCRIPTION
MIN
1
tw(ENDATx_IN)
Pulse width, ENDATx_IN
40
MAX UNIT
ns
Table 7-137. PRU-ICSS PRU Switching Requirements - EnDAT Mode
NO. PARAMETER
DESCRIPTION
MIN
2
tw(ENDATx_CLK)
Pulse width, ENDATx_CLK
20
3
td(ENDATx_OUT-
Delay time, ENDATx_CLK fall to ENDATx_OUT
-10
ENDATx_CLK)
4
td(ENDATx_OUT_EN- Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN
-10
ENDATx_CLK)
MAX
10
UNIT
ns
ns
10 ns
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Timing Requirements and Switching Characteristics 331
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