AM5718_17 Datasheet, PDF (218/396 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

AM5718, AM5716
SPRS957D – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 7-14. DPI Video Output i (i = 1..3) Default Switching Characteristics (continued)
NO.
PARAMETE
R
DESCRIPTION
D2 t_w(clkL)
Pulse duration, output pixel clock vouti_clk low
MODE
MIN
P*0.5-1
(1)
MAX
UNIT
ns
D3 t_w(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
(1)
D5 t_d(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
-2.5
2.5
ns
D6 t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI1
-2.5
2.5
ns
D5 t_d(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output DPI2 (vin2a_fld0 clock -2.5
2.5
ns
data vouti_d[23:0] valid
reference)
D6 t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output DPI2 (vin2a_fld0 clock -2.5
2.5
ns
control signals vouti_vsync, vouti_hsync, vouti_de, and
reference)
vouti_fld valid
D5 t_d(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output DPI2 (xref_clk2 clock
-2.5
2.5
ns
data vouti_d[23:0] valid
reference)
D6 t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output DPI2 (xref_clk2 clock
-2.5
2.5
ns
control signals vouti_vsync, vouti_hsync, vouti_de, and
reference)
vouti_fld valid
D5 t_d(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
-2.5
2.5
ns
D6 t_d(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI3
-2.5
2.5
ns
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
Table 7-15. DPI Video Output i (i = 1..3) Alternate Switching Characteristics⁽²⁾
NO.
PARAMETE
R
DESCRIPTION
D1 t_c(clk)
Cycle time, output pixel clock vouti_clk
D2 t_w(clkL)
D3 t_w(clkH)
D5 t_d(clk-ctlV)
D6 t_d(clk-dV)
D5 t_d(clk-ctlV)
D6 t_d(clk-dV)
D5 t_d(clk-ctlV)
D6 t_d(clk-dV)
D5 t_d(clk-ctlV)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
MODE
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
DPI1/3 in 3.3V mode
DPI1
MIN
6.06⁽³⁾
13.33⁽³⁾
P*0.5-1
(1)
P*0.5-1
(1)
1.51
MAX
4.55
DPI1
1.51 4.55
DPI2 (vin2a_fld0 clock 1.51 4.55
reference)
DPI2 (vin2a_fld0 clock 1.51 4.55
reference)
DPI2 (xref_clk2 clock
reference)
DPI2 (xref_clk2 clock
reference)
1.51 4.55
1.51 4.55
DPI3
1.51 4.55
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
218 Timing Requirements and Switching Characteristics
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