THS4500IDR Datasheet, PDF (33/48 Pages) Texas Instruments – WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS

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6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This process results
in a part that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
exceeded. For best performance, design for a
maximum junction temperature of +125°C. Between
+125°C and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power
dissipation for a given package can be calculated
using the following formula.
P
= ^{TMAX - TA}
Dmax
q
JA
Where:
P_Dmax is the maximum power dissipation in the
amplifier (W).
T_MAX is the absolute maximum junction
temperature (°C).
T_A is the ambient temperature (°C).
θ_JA = θ_JC + θ_CA
θ_JC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θ_CA is the thermal coefficient from the case to
ambient air (°C/W).
(28)
For systems where heat dissipation is more critical,
the THS4500 family of devices is offered in an
MSOP-8 package with PowerPAD. The thermal
coefficient for the MSOP PowerPAD package is
substantially improved over the traditional SOIC.
THS4500
THS4501
SLOS350F – APRIL 2002 – REVISED OCTOBER 2011
Maximum power dissipation levels are depicted in
Figure 114 for the two packages. The data for the
DGN package assumes a board layout that follows
the PowerPAD layout guidelines referenced above
and detailed in the PowerPAD application notes in
the Additional Reference Material section at the end
of the data sheet.
3.5
8-Pin DGN Package
3
2.5
2
8-Pin D Package
1.5
1
0.5
0
−40 −20 0
20 40 60 80
T_A − Ambient Temperature − °C
θ_JA = 170°C/W for 8-Pin SOIC (D)
θ_JA = 58.4°C/W for 8-Pin MSOP (DGN)
Τ_J = 150°C, No Airflow
Figure 114. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this consideration is difficult to quantify
because the signal pattern is inconsistent; an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however,
the load capacitance should be isolated by two
isolation resistors in series with the output. The
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
to begin the optimization process. Larger isolation
resistors decrease the amount of peaking in the
frequency response induced by the capacitive load,
but this decreased peaking comes at the expense ofa
larger voltage drop across the resistors, increasing
the output swing requirements of the system.
Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
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