THS4500IDR Datasheet, PDF (2/48 Pages) Texas Instruments – WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS

THS4500
THS4501
SLOS350F – APRIL 2002 – REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, V_S
Input voltage, V_I
Output current, I_O ⁽²⁾
Differential input voltage, V_ID
Continuous power dissipation
Maximum junction temperature, T_J ⁽³⁾
Maximum junction temperature, continuous operation, long-term reliability, T_J
Operating free-air temperature range, T_A ⁽⁴⁾
C suffix
I suffix
Storage temperature range, T_stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
ESD rating:
CDM
MM
UNIT
16.5 V
±V_S
150 mA
4V
See Dissipation Rating Table
+150°C
+125°C
0°C to +70°C
–40°C to +85°C
–65°C to +150°C
+300°C
4000 V
1000 V
100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The THS4500/1 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS TABLE
PACKAGE
D (8-pin)
DGN (8-pin)
DGK (8-pin)
θ_JC
(°C/W)
38.3
4.7
54.2
θ_JA ⁽¹⁾
(°C/W)
97.5
58.4
260
POWER RATING⁽²⁾
T_A ≤ +25°C
1.02 W
T_A = +85°C
410 mW
1.71 W
685 mW
385 mW
154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage
Operating free- air temperature, T_A
Dual supply
Single supply
C suffix
I suffix
MIN
NOM
MAX
UNIT
±5
±7.5
V
4.5
5
15
0
+70
°C
–40
+85
2
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