BQ24295 Datasheet, PDF (33/45 Pages) Texas Instruments – I2C Controlled 3A Single Cell USB Charger

bq24295
www.ti.com
SLUSBC1 – SEPTEMBER 2013
Input Over-Voltage (ACOV)
The maximum input voltage for buck mode operation is V_{VBUS_OP}. If VBUS voltage exceeds V_ACOV, the device
stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An
INT is asserted to the host.
System Over-Voltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to
clamp the overshoot.
Current Monitoring in Boost Mode
The bq24295 closely monitors LSFET current to ensure safe boost mode operation.
Battery Protection
Battery Over-Voltage Protection (BATOVP)
The battery over-voltage limit is clamped at V_{BAT_OVP} (4% nominal) above the battery regulation voltage. When
battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[5] goes
high and an INT is asserted to the host.
Battery Short Protection
If the battery voltage falls below V_short (2V typical), the device immediately turns off BATFET to disable the
battery charging or supplement mode. 1ms later, the BATFET turns on and charge the battery with 100mA
current. The device does not turn on BATFET to discharge a battery that is below 2.5V.
System Over-Current Protection
If the system is shorted or exceeds the over-current limit, the device latches off BATFET. DC source insertion on
VBUS is required to reset the latch-off condition and turn on BATFET.
Serial Interface
The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C^TM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor. The I²C interface supports both standard mode (up to 100kbits), and
fast mode (up to 400kbits).
Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-
up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: bq24295
Submit Documentation Feedback
33