BQ24295 Datasheet, PDF (12/45 Pages) Texas Instruments – I2C Controlled 3A Single Cell USB Charger

bq24295
SLUSBC1 – SEPTEMBER 2013
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ELECTRICAL CHARACTERISTICS (continued)
V_{VBUS_UVLOZ} < V_VBUS < V_ACOV and V_VBUS > V_BAT + V_SLEEP, T_J = –40°C to 125°C and T_J = 25°C for typical values unless other
noted.
PARAMETER
BOOST MODE OPERATION
V_{OTG_REG}
V_{OTG_REG_ACC}
V_{OTG_BAT}
I_OTG
V_{OTG_OVP}
V_{OTG_OVP_HYS}
I_{OTG_LSOCP}
I_{OTG_HSZCP}
REGN LDO
Boost mode output voltage
Boost mode output voltage accuracy
Battery voltage exiting boost mode
Boost mode output current on PMID
OTG over-voltage threshold
OTG over-voltage threshold hysteresis
LSFET cycle by cycle current limit
HSFET under current falling threshold
V_REGN
REGN LDO output voltage
I_REGN
QON Timing
REGN LDO current limit
t_QON
QON pin high time to turn on BATFET
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON)
V_ILO
V_IH
V_{OUT_LO}
I_BIAS
Input low threshold
Input high threshold
Output low saturation voltage
High level leakage current (OTG, CE, STAT
)
I_BIAS
High level leakage current (QON)
I²C INTERFACE (SDA, SCL, INT)
V_IH
Input high threshold level
V_IL
Input low threshold level
V_OL
Output low threshold level
I_BIAS
High-level leakage current
f_SCL
SCL clock frequency
DIGITAL CLOCK AND WATCHDOG TIMER
f_HIZ
Digital crude clock
f_DIG
Digital clock
t_WDT
REG05[5:4]=11
TEST CONDITIONS
I(PMID) = 0, REG06[7:4]=1001 (5.126V)
I(PMID) = 0, REG06[7:4]=1001 (5.126V)
BAT falling, REG04[1]=1
Rising Threshold
Falling Threshold
V_VBUS = 6V, I_REGN = 40mA
V_VBUS = 5V, I_REGN = 20mA
V_VBUS = 5V, V_REGN = 3.8V
Sink current = 5 mA
Pull up rail 1.8V
Pull up rail 3.6V
VPULL-UP = 1.8V, SDA and SCL
VPULL-UP = 1.8V, SDA and SCL
Sink current = 5mA
VPULL-UP = 1.8V, SDA and SCL
REGN LDO disabled
REGN LDO enabled
REGN LDO disabled
REGN LDO enabled
MIN TYP
MAX UNITS
5.12
-3
2.9
1.3
5.8
6
300
5
100
V
3%
V
A
V
mV
A
mA
4.8
5
4.7
4.8
50
5.5 V
V
mA
2
ms
0.4 V
1.3
V
0.4 V
1 µA
8 µA
1.3
V
0.4 V
0.4 V
1 µA
400 kHz
15
1300
112
136
35
1500
160
160
50 kHz
1700 kHz
sec
Figure 2. I²C-Compatible Interface Timing Diagram
12
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