THS7372 Datasheet, PDF (32/49 Pages) Texas Instruments – 4-Channel Video Amplifier with One CVBS and Three Full-HD Filters with 6-dB Gain

THS7372
SBOS578 – AUGUST 2011
www.ti.com
To help minimize this input signal overshoot problem, the control loop in the THS7372 has an internal low-pass
filter, as shown in Figure 86. This filter reduces the response time of the STC circuit. This delay is a function of
how far the voltage is below ground, but in general it is approximately a 400-ns delay for the SD channel filters
and approximately a 150-ns delay for the FHD filters. The effect of this filter is to slow down the response of the
control loop so as not to clamp on the input overshoot voltage but rather the flat portion of the sync signal.
Input
0.1 mF ^Input
Pin
+V_S
+V_S
STC LPF
g_m
800 kW
Internal
Circuitry
Level
Shift
Figure 86. Equivalent AC Sync-Tip-Clamp Input Circuit
As a result of this delay, sync may have an apparent voltage shift. The amount of shift depends on the amount of
droop in the signal as dictated by the input capacitor and the STC current flow. Because sync is used primarily
for timing purposes with syncing occurring on the edge of the sync signal, this shift is transparent in most
systems.
While this feature may not fully eliminate overshoot issues on the input signal, in cases of extreme overshoot
and/or ringing, the STC system should help minimize improper clamping levels. As an additional method to help
minimize this issue, an external capacitor (for example, 10 pF to 47 pF) to ground in parallel with the external
termination resistors can help filter overshoot problems.
It should be noted that this STC system is dynamic and does not rely upon timing in any way. It only depends on
the voltage that appears at the input pin at any given point in time. The STC filtering helps minimize level shift
problems associated with switching noises or very short spikes on the signal line. This architecture helps ensure
a very robust STC system.
When the ac STC operation is used, there must also be some finite amount of discharge bias current. As
previously described, if the input signal goes below the 0-V clamp level, the internal loop of the THS7372
sources current to increase the voltage appearing at the input pin. As the difference between the signal level and
the 0-V reference level increases, the amount of source current increases proportionally—supplying up to 6 mA
of current. Thus, the time to re-establish the proper STC voltage can be very fast. If the difference is very small,
then the source current is also very small to account for minor voltage droop.
However, what happens if the input signal goes above the 0-V input level? The problem is that the video signal is
always above this level and must not be altered in any way. Thus, if the sync level of the input signal is above
this 0-V level, then the internal discharge (sink) current reduces the ac-coupled bias signal to the proper 0-V
level.
This discharge current must not be large enough to alter the video signal appreciably or picture quality issues
may arise. This effect is often seen by looking at the tilt (droop) of a constant luma signal being applied and the
resulting output level. The associated change in luma level from the beginning and end of the video line is the
amount of line tilt (droop).
If the discharge current is very small, the amount of tilt is very low, which is a generally a good thing. However,
the amount of time for the system to capture the sync signal could be too long. This effect is also termed hum
rejection. Hum arises from the ac line voltage frequency of 50 Hz or 60 Hz. The value of the discharge current
and the ac-coupling capacitor combine to dictate the hum rejection and the amount of line tilt.
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