THS7372 Datasheet, PDF (29/49 Pages) Texas Instruments – 4-Channel Video Amplifier with One CVBS and Three Full-HD Filters with 6-dB Gain

THS7372
www.ti.com
SBOS578 – AUGUST 2011
INPUT OVERVOLTAGE PROTECTION
The THS7372 is built using a very high-speed, complementary, bipolar, and CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 83.
+V_S
External
Input/Output
Pin
Internal
Circuitry
Figure 83. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. The
protection diodes can typically support 30 mA of continuous current when overdriven.
TYPICAL CONFIGURATION AND VIDEO TERMINOLOGY
A typical application circuit using the THS7372 as a video buffer is shown in Figure 84. It shows a DAC or
encoder driving the input channels of the THS7372. The SD channel (CVBS IN pin) can be used for NTSC, PAL,
or SECAM signals. The other three channels are the component video Y’/P’_B/P’_R (sometimes labeled Y’U’V’ or
incorrectly labeled Y’/C’_B/C’_R) signals. These signals are typically 480i, 576i, 480p, 576p, 720p, 1080i, or up to
1080p60 signals.
Note that the Y’ term is used for the luma channels throughout this document rather than the more common
luminance (Y) term. This usage accounts for the definition of luminance as stipulated by the International
Commission on Illumination (CIE). Video departs from true luminance because a nonlinear term, gamma, is
added to the true RGB signals to form R’G’B’ signals. These R’G’B’ signals are then used to mathematically
create luma (Y’). Thus, luminance (Y) is not maintained, providing a difference in terminology.
CVBS
Y'/G'
37.4 W
+2.7 V to
+5 V
37.4 W
THS7372
1 CVBS IN
2 NC
3 ^VS+
4 NC
5 FHD1 IN
CVBS OUT 14
DIS CVBS 13
GND 12
DIS FHD 11
FHD1 OUT 10
Disable
CVBS
Disable
FHD
CVBS Out
75 W
Y'/G’ Out
75 W
75 W
75 W
P’_B/B'
37.4 W
6 FHD2 IN
7 FHD3 IN
FHD2 OUT 9
FHD3 OUT 8
P'_B/B’ Out
75 W
75 W
P’_R/R'
37.4 W
P'_R/R’ Out
75 W
75 W
Figure 84. Typical Four-Channel System Inputs from DC-Coupled Encoder/DAC with
DC-Coupled Line Driving
Copyright © 2011, Texas Instruments Incorporated
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