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TDA2EG-17 Datasheet, PDF (315/391 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 17mm Package (CBD Package) Silicon Revision 2.0 | |||
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TDA2EG-17
SPRS969B â AUGUST 2016 â REVISED JUNE 2017
⢠Power and clock management
â Debugger can get the status of the power domain associated to each TAP.
â Debugger may prevent the application software switching off the power domain.
â Application power management behavior can be preserved during debug across power transitions.
â For more information, see Power and Clock Management section of the Device TRM.
⢠Reset management
â Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.
â For more information, see Reset Management section of the Device TRM.
⢠Cross-triggering
â Provides a way to propagate debug (trigger) events from one processor, subsystem, or module to
another:
⢠Subsystem A can be programmed to generate a debug event, which can then be exported as a
global trigger across the device.
⢠Subsystem B can be programmed to be sensitive to the trigger line input and to generate an
action on trigger detection.
â Two global trigger lines are implemented
â Device-level cross-triggering is handled by the XTRIG (TI cross-trigger) module implemented in the
debug subsystem
â Various ARM® CoreSight⢠cross-trigger modules implemented to provide support for CoreSight
triggers distribution
⢠CoreSight Cross-Trigger Interface (CS_CTI) modules
⢠CoreSight Cross-Trigger Matrix (CS_CTM) modules
â For more information about cross-triggering, see Cross-Triggering section of the Device TRM.
⢠Suspend
â Provides a way to stop a closely coupled hardware process running on a peripheral module when
the host processor enters debug state
â For more information about suspend, see Suspend section of the Device TRM.
⢠MPU watchpoint
â Embedded in MPU subsystem
â Provides visibility on MPU to EMIF direct paths
â For more information, see MPU Memory Adaptor (MPU_MA) Watchpoint section of the Device
TRM.
⢠Processor trace
â Cortex-A15 (MPU) and C66x (DSP) processor trace is supported
â Program trace only for MPU (no data trace)
â MPU trace supported by a CoreSight Program Trace Macrocell (CS_PTM) module
â Three exclusive trace sinks:
⢠CoreSight Trace Port Interface Unit (CS_TPIU) â trace export to an external trace receiver
⢠CTools Trace Buffer Router (CT_TBR) in system bridge mode â trace export through USB
⢠CT_TBR in buffer mode â trace history store into on-chip trace buffer
â For more information, see Processor Trace section of the Device TRM.
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Detailed Description 315
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