TDA2EG-17 Datasheet, PDF (201/391 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 17mm Package (CBD Package) Silicon Revision 2.0

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TDA2EG-17
SPRS969B – AUGUST 2016 – REVISED JUNE 2017
• 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
• Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
• Break character detection and generation
• Configurable data format:
– Data bit: 5, 6, 7, or 8 bits
– Parity bit: Even, odd, none
– Stop-bit: 1, 1.5, 2 bit(s)
• Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
• Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
• Only UART3 supports IrDA
NOTE
For more information, see the UART section of the Device TRM.
Table 5-54, Table 5-55 and Figure 5-37 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 5-54. Timing Requirements for UART
NO.
PARAMETER
DESCRIPTION
4 t_w(RX)
5 t_w(CTS)
t_d(RTS-TX)
t_d(CTS-TX)
Pulse width, receive data bit, 15/30/100pF high or low
Pulse width, receive start bit, 15/30/100pF high or low
Delay time, transmit start bit to transmit data
Delay time, receive start bit to transmit data
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
MIN
0.96U⁽¹⁾
0.96U⁽¹⁾
P⁽²⁾
P⁽²⁾
MAX
1.05U⁽¹⁾
1.05U⁽¹⁾
UNIT
ns
ns
ns
ns
Table 5-55. Switching Characteristics Over Recommended Operating Conditions for UART
NO. PARAMETER
DESCRIPTION
15 pF
f_(baud)
Maximum programmable baud rate
30 pF
100 pF
2 t_w(TX)
3 t_w(RTS)
Pulse width, transmit data bit, 15/30/100 pF high or low
Pulse width, transmit start bit, 15/30/100 pF high or low
(1) U = UART baud time = 1/programmed baud rate
MIN
U - 2⁽¹⁾
U - 2⁽¹⁾
MAX
12
0.23
0.115
U + 2⁽¹⁾
U + 2⁽¹⁾
UNIT
MHz
ns
ns
UARTi_TXD
3
2
Start
Bit
Data Bits
UARTi_RXD
5
4
Start
Bit
Data Bits
Figure 5-37. UART Timing
SPRS906_TIMING_UART_01
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Specifications 201