TDA2EG-17 Datasheet, PDF (309/391 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 17mm Package (CBD Package) Silicon Revision 2.0

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TDA2EG-17
SPRS969B – AUGUST 2016 – REVISED JUNE 2017
• Address Lookup Engine (ALE)
– 1024 total address entries plus VLANs
– Wire rate lookup
– Host controlled time-based aging
– Multiple spanning tree support (spanning tree per VLAN)
– L2 address lock and L2 filtering support
– MAC authentication (802.1x)
– Receive-based or destination-based multicast and broadcast rate limits
– MAC address blocking
– Source port locking
– OUI (Vendor ID) host accept/deny feature
– Remapping of priority level of VLAN or ports
• VLAN support
– 802.1Q compliant
• Auto add port VLAN for untagged frames on ingress
• Auto VLAN removal on egress and auto pad to minimum frame size
• Ethernet Statistics:
– EtherStats and 802.3Stats Remote network Monitoring (RMON) statistics gathering (shared)
– Programmable statistics interrupt mask when a statistic is above one half its 32-bit value
• Flow Control Support (802.3x)
• Digital loopback and FIFO loopback modes supported
• Maximum frame size 2016 bytes (2020 with VLAN)
• 8k (2048 × 32) internal CPPI buffer descriptor memory
• Management Data Input/Output (MDIO) module for PHY Management
• Programmable interrupt control with selected interrupt pacing
• Emulation support
• Programmable Transmit Inter Packet Gap (IPG)
• Reset isolation (switch function remains active even in case of all device resets except for POR pin
reset and ICEPICK cold reset)
• Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps.
• IEEE 802.3 gigabit Ethernet conformant
For more information, see section Gigabit Ethernet Switch (GMAC_SW) in chapter Serial Communication
Interfaces of the device TRM.
6.13.13 eMMC/SD/SDIO
The eMMC/SD/SDIO host controller provides an interface between a local host (LH) such as a
microprocessor unit (MPU) or digital signal processor (DSP) and either eMMC, SD® memory cards, or
SDIO cards and handles eMMC/SD/SDIO transactions with minimal LH intervention.
Optionally, the controller is connected to the L3_MAIN interconnect to have a direct access to system
memory. It also supports two direct memory access (DMA) slave channels or a DMA master access (in
this case, slave DMA channels are deactivated) depending on its integration.
The eMMC/SD/SDIO host controller deals with eMMC/SD/SDIO protocol at transmission level, data
packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical correctness.
The application interface can send every eMMC/SD/SDIO command and poll for the status of the adapter
or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation.
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