LM3S9BN5 Datasheet, PDF (304/1380 Pages) Texas Instruments – Stellaris® LM3S9BN5 Microcontroller

System Control
Register 38: Software Reset Control 2 (SRCR2), offset 0x048
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31
30
29
28
27
26
reserved
EMAC0
Type RO
RO
RO
R/W
RO
RO
Reset
0
0
0
0
0
0
15
14
13
12
reserved
UDMA
Type RO
Reset
0
RO
R/W
RO
0
0
0
11
10
reserved
RO
RO
0
0
25
24
23
22
21
20
19
18
17
16
reserved
USB0
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
28
27:17
16
15:14
13
12:9
8
Name
reserved
EMAC0
reserved
USB0
reserved
UDMA
reserved
GPIOJ
Type
RO
R/W
RO
R/W
RO
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MAC0 Reset Control
When this bit is set, Ethernet MAC layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB0 Reset Control
When this bit is set, USB module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Reset Control
When this bit is set, uDMA module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port J Reset Control
When this bit is set, Port J module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
304
January 21, 2012
Texas Instruments-Production Data