LM3S9BN5 Datasheet, PDF (1175/1380 Pages) Texas Instruments – Stellaris® LM3S9BN5 Microcontroller

Stellaris^® LM3S9BN5 Microcontroller
Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C
Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC
Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC
Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C
If the MINFLTPER bit in the PWMnCTL register is set, this register specifies the 16-bit time-extension
value to be used in extending the fault condition. The value is loaded into a 16-bit down counter,
and the counter value is used to extend the fault condition. The fault condition is released in the
clock immediately after the counter value reaches 0. The fault condition is asynchronous to the
PWM clock; and the delay value is the product of the PWM clock period and the (MFP field value
+ 1) or (MFP field value + 2) depending on when the fault condition asserts with respect to the PWM
clock. The counter decrements at the PWM clock rate, without pause or condition.
PWM0 Minimum Fault Period (PWM0MINFLTPER)
PWM0 base: 0x4002.8000
Offset 0x07C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MFP
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15:0
Name
reserved
MFP
Type
RO
R/W
Reset
0x0000
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Minimum Fault Period
The number of PWM clocks by which a fault condition is extended when
the delay is enabled by PWMnCTL MINFLTPER.
January 21, 2012
Texas Instruments-Production Data
1175