|
XPC8255ZUIFBC Datasheet, PDF (3/41 Pages) Texas Instruments – PowerQUICC II Integrated Communications Processor Hardware Specifications | |||
|
◁ |
Features
â Common on-chip processor (COP) test interface
â High-performance (4.4â5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
â Supports bus snooping for data cache coherency
â Floating-point unit (FPU)
⢠Separate power supply for internal logic and for I/O
⢠Separate PLLs for G2 core and for the CPM
â G2 core and CPM can run at different frequencies for power/performance optimization
â Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
â Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
⢠64-bit data and 32-bit address 60x bus
â Bus supports multiple master designs
â Supports single- and four-beat burst transfers
â 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
â Supports data parity or ECC and address parity
⢠32-bit data and 18-bit address local bus
â Single-master bus, supports external slaves
â Eight-beat burst transfers
â 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
⢠System interface unit (SIU)
â Clock synthesizer
â Reset controller
â Real-time clock (RTC) register
â Periodic interrupt timer
â Hardware bus monitor and software watchdog timer
â IEEE Std 1149.1⢠JTAG test access port
⢠Twelve-bank memory controller
â Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
â Byte write enables and selectable parity generation
â 32-bit address decodes with programmable bank size
â Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
â Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
â Dedicated interface logic for SDRAM
⢠CPU core can be disabled and the device can be used in slave mode to an external core
⢠Communications processor module (CPM)
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3
|
▷ |