TNETA1500 Datasheet, PDF (3/29 Pages) Texas Instruments – 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

TNETA1500
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
functional block diagram
CRCAP
SDNS021D – MARCH 1994 – REVISED JANUARY 1998
Receive Operation
RSDT
RSDC
CKRECBP
RSCT
RSCC
CLKLOOP
OE
RESET
0.1-µF Capacitor
FLB
Connected Externally
8KHZREF LOF LOS OOF
Clock
Recovery
Framing and
Serial-to-Parallel
Conversion
B1ERR
LOP
LAIS LFERF LOSRD LOCA
Descrambling,
B1-Parity,
Alarm
Generation
Demux
8
ATM-Cell
Extraction
and
Descrambling
RD0–RD7
RCKI
RXCELL
RRE
RXFE
Controller
Interface
8 _D0–D7
8
A0–A7
READY
RD/WR
INTR
SEL
FLAGT
FLAGC
TSDT
TSDC
TSCT
TSCC
TLB
CKGENBP
TXREFCK
TXHCKT
TXHCKC
Parallel-to-Serial
Conversion
Scrambling
and
B1-Parity
Generation
Mux
Transmit Operation
Clock
Generation
CGCAP
0.1-µF Capacitor
Connected Externally
SDHENABLE
ATM-Cell
8 _TD0–TD7
Scrambling
TCKI
and
TXCELL
Cell Insertion
TWE
TXAF
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