TNETA1500 Datasheet, PDF (24/29 Pages) Texas Instruments – 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

TNETA1500
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS021D – MARCH 1994 – REVISED JANUARY 1998
switching characteristics (see Figure 5)
NO.
1 tw(8KHZREFL) Pulse duration, 8KHZREF low
8KHZREF
(output)
1
Figure 5. 8-kHz Reference Signal
MIN MAX UNIT
22
27 ns
APPLICATION INFORMATION
introduction
The TNETA1500 SONET/SDH ATM BiCMOS receiver/transmitter is designed to insert/extract ATM cells
into/from a 155.52-Mbit/s STS-3c/STM-1 frame. The device contains two APLLs and the digital logic necessary
to process the incoming frame and build the output frame. The two APLLs are used to:
D Recover a 155.52-MHz receive clock from the incoming serial-data stream
D Generate a 155.52-MHz transmit clock from an external 19.44-MHz signal
The device is fabricated from a 0.8-micron BiCMOS process. The BiCMOS process provides the capability of
designing true differential PECL (ECL referenced to 5 V instead of ground) serial inputs and outputs. The
advantages of providing true PECL inputs and outputs are:
D The device interfaces directly to fiber-optic receivers and transmitters and UTP-5 transceivers without
external buffering.
D The device outputs can directly drive a 50-Ω line terminated with 50 Ω to 3 V or the Thevenin equivalent
(121 Ω to ground and 82 Ω to V_CC). This eliminates transmission-line reflections and improves
performance.
D The differential PECL inputs provide a high common-mode noise-rejection ratio (CMRR), which improves
noise immunity of the device.
D The reduced output voltage swing of the differential PECL outputs (approximately 800 mV) reduces the
internal noise generated when the high-speed serial outputs switch. This is especially important since the
outputs are switching at 155.52 Mbit/s.
Internally, the two APLLs are isolated from each other and the digital logic blocks (see Figure 6). Each APLL
has its own V_CC and ground connections that are not connected internally to the V_CC and ground connections
of the other blocks. From a power and ground connection viewpoint, this forms three blocks: the digital logic
block, the analog clock-recovery block, and the analog clock-generation block.
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