TNETA1500 Datasheet, PDF (1/29 Pages) Texas Instruments – 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

TNETA1500
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
D Single-Chip Receiver/Transmitter for
Transporting 53-Byte ATM Cells Via
STS-3c/STM-1 Frame (155.52 Mbit/s)
D On-Chip Analog Phase-Locked Loop
(APLL) Provides:
– Recovery of Receive Clock From
Incoming Serial-Data Stream
– Transmit Clock Generation From
External 19.44-MHz Clock Source
D Inserts and Extracts ATM Cells Into/From
SONET/SDH STS-3c/STM-1 SPE
D Detects Multiple-Bit Errors and Corrects
Single-Bit Errors in the 5-Byte ATM
Headers of Incoming ATM Cells
SDNS021D – MARCH 1994 – REVISED JANUARY 1998
D Generates Alarms for:
– Loss of Incoming Serial Signal (LOS)
– Out of Frame (OOF)
– Loss of Frame (LOF)
– B1-Byte Parity Error (B1ERR)
– Loss of ATM Cell Alignment (LOCA)
– Line Far-End Receive Failure (LFERF)
– Receive Loss of Pointer (LOP)
– Line Alarm Indication Signal (LAIS)
D Meets ATM Forum ATM User-Network
Interface Specification Requirement
D BiCMOS Device Packaged in a 144-Pin
Plastic Quad Flat Package (PQFP) or a
144-Pin Thin Quad Flat Package (TQFP)
description
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode
(ATM) line-interface receiver/transmitter provides a single-chip implementation for transporting ATM cells over
the SONET/SDH network at the STS-3c/STM-1 rate of 155.52 Mbit/s. This device provides all the functionality
required to insert and extract 53-byte ATM cells into/from an STS-3c/STM-1 synchronous payload envelope
(SPE), including clock recovery and clock generation using analog phase-locked loops (APLL).
On the receive side, the TNETA1500 accepts 155.52-Mbit/s serial data, recovers the embedded clock signal,
performs SONET/SDH frame alignment and serial-to-parallel conversion, identifies the SONET/SDH payload,
and establishes the ATM-cell boundaries. The ATM cells are extracted from the payload, descrambled, and
passed to the receive output FIFO for output to the next device (i.e., a reassembly device). On the transmit side,
complete 53-byte ATM cells are placed into the transmit input FIFO, scrambled, and inserted into an
STS-3c/STM-1 SPE. The SONET/SDH frame is scrambled and converted to a serial-data stream for output.
An APLL is used to generate the 155.52-MHz output clock from a low-speed 19.44-MHz oscillator, eliminating
the need for a high-speed 155.52-MHz oscillator.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1998, Texas Instruments Incorporated
1