TMS417800A Datasheet, PDF (3/24 Pages) Texas Instruments – 2097152 BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY

functional block diagram
TMS417800A
2097152 BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997
RAS CAS W OE
Timing and Control
A0
A1
10
Column Decode
Column-
Sense Amplifiers
8
Address
Buffers
A9
256K Array _R 256K Array
256K Array ^o 256K Array
w
8
Data-
In
8
Reg.
I/O
32
Row-
D
e
Buffers
8
32
Data-
Address ₁₁
Buffers
c
o
Out
Reg.
d
A10
256K Array e 256K Array
DQ0 – DQ7
11
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup-and-hold, and for address multiplexing, is
eliminated. The maximum number of columns that can be accessed is determined by t_RASP , the maximum
row-address strobe (RAS) low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while column-address strobe (CAS)
is high. The falling edge of CAS latches the column addresses and enables the output, which allows the devices
to operate at a higher data bandwidth than conventional page-mode devices because data retrieval begins as
soon as the column address is valid rather than when CAS goes low. This performance improvement is referred
to as enhanced-page mode. A valid column address can be presented immediately after row-address hold time
has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after t_CAC
max (access time from CAS low) if t_AA max (access time from column address) and t_RAC (access time from RAS)
have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes high,
access time for the next cycle is determined by the later occurrence of t_CPA (access time from CAS precharge)
or t_CAC.
address: A0 – A10
Twenty-one address bits are required to decode each of the 2 097 152 storage cell locations. Eleven
row-address bits are set up on inputs A0 through A10 and latched on the chip by RAS. Ten column-address bits
are set up on A0 through A9. All addresses must be stable on or before the falling edges of RAS and CAS. RAS
is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip select, activating the output buffers and latching the address bits into the column-address buffers.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
3